- mem: type of memory access for the data at the time of the sample
        - snoop: type of snoop (if any) for the data at the time of the sample
        - dcacheline: the cacheline the data address is on at the time of the sample
+       - phys_daddr: physical address of data being executed on at the time of sample
 
        And the default sort keys are changed to local_weight, mem, sym, dso,
        symbol_daddr, dso_daddr, snoop, tlb, locked, see '--mem-mode'.
 
                        symlen = unresolved_col_width + 4 + 2;
                        hists__set_unres_dso_col_len(hists, HISTC_MEM_DADDR_DSO);
                }
+
+               hists__new_col_len(hists, HISTC_MEM_PHYS_DADDR,
+                                  unresolved_col_width + 4 + 2);
+
        } else {
                symlen = unresolved_col_width + 4 + 2;
                hists__new_col_len(hists, HISTC_MEM_DADDR_SYMBOL, symlen);
 
        HISTC_GLOBAL_WEIGHT,
        HISTC_MEM_DADDR_SYMBOL,
        HISTC_MEM_DADDR_DSO,
+       HISTC_MEM_PHYS_DADDR,
        HISTC_MEM_LOCKED,
        HISTC_MEM_TLB,
        HISTC_MEM_LVL,
 
        ams->al_addr = al.addr;
        ams->sym = al.sym;
        ams->map = al.map;
+       ams->phys_addr = 0;
 }
 
 static void ip__resolve_data(struct thread *thread,
-                            u8 m, struct addr_map_symbol *ams, u64 addr)
+                            u8 m, struct addr_map_symbol *ams,
+                            u64 addr, u64 phys_addr)
 {
        struct addr_location al;
 
        ams->al_addr = al.addr;
        ams->sym = al.sym;
        ams->map = al.map;
+       ams->phys_addr = phys_addr;
 }
 
 struct mem_info *sample__resolve_mem(struct perf_sample *sample,
                return NULL;
 
        ip__resolve_ams(al->thread, &mi->iaddr, sample->ip);
-       ip__resolve_data(al->thread, al->cpumode, &mi->daddr, sample->addr);
+       ip__resolve_data(al->thread, al->cpumode, &mi->daddr,
+                        sample->addr, sample->phys_addr);
        mi->data_src.val = sample->data_src;
 
        return mi;
 
        if (sample_type & PERF_SAMPLE_DATA_SRC)
                printf(" . data_src: 0x%"PRIx64"\n", sample->data_src);
 
+       if (sample_type & PERF_SAMPLE_PHYS_ADDR)
+               printf(" .. phys_addr: 0x%"PRIx64"\n", sample->phys_addr);
+
        if (sample_type & PERF_SAMPLE_TRANSACTION)
                printf("... transaction: %" PRIx64 "\n", sample->transaction);
 
 
        .se_width_idx   = HISTC_MEM_DCACHELINE,
 };
 
+static int64_t
+sort__phys_daddr_cmp(struct hist_entry *left, struct hist_entry *right)
+{
+       uint64_t l = 0, r = 0;
+
+       if (left->mem_info)
+               l = left->mem_info->daddr.phys_addr;
+       if (right->mem_info)
+               r = right->mem_info->daddr.phys_addr;
+
+       return (int64_t)(r - l);
+}
+
+static int hist_entry__phys_daddr_snprintf(struct hist_entry *he, char *bf,
+                                          size_t size, unsigned int width)
+{
+       uint64_t addr = 0;
+       size_t ret = 0;
+       size_t len = BITS_PER_LONG / 4;
+
+       addr = he->mem_info->daddr.phys_addr;
+
+       ret += repsep_snprintf(bf + ret, size - ret, "[%c] ", he->level);
+
+       ret += repsep_snprintf(bf + ret, size - ret, "%-#.*llx", len, addr);
+
+       ret += repsep_snprintf(bf + ret, size - ret, "%-*s", width - ret, "");
+
+       if (ret > width)
+               bf[width] = '\0';
+
+       return width;
+}
+
+struct sort_entry sort_mem_phys_daddr = {
+       .se_header      = "Data Physical Address",
+       .se_cmp         = sort__phys_daddr_cmp,
+       .se_snprintf    = hist_entry__phys_daddr_snprintf,
+       .se_width_idx   = HISTC_MEM_PHYS_DADDR,
+};
+
 static int64_t
 sort__abort_cmp(struct hist_entry *left, struct hist_entry *right)
 {
        DIM(SORT_MEM_LVL, "mem", sort_mem_lvl),
        DIM(SORT_MEM_SNOOP, "snoop", sort_mem_snoop),
        DIM(SORT_MEM_DCACHELINE, "dcacheline", sort_mem_dcacheline),
+       DIM(SORT_MEM_PHYS_DADDR, "phys_daddr", sort_mem_phys_daddr),
 };
 
 #undef DIM
 
        SORT_MEM_SNOOP,
        SORT_MEM_DCACHELINE,
        SORT_MEM_IADDR_SYMBOL,
+       SORT_MEM_PHYS_DADDR,
 };
 
 /*
 
        struct symbol *sym;
        u64           addr;
        u64           al_addr;
+       u64           phys_addr;
 };
 
 struct branch_info {