amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
                amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
                amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
                break;
        default:
                return -EINVAL;
 
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
+MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
 
 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
 
        case CHIP_NAVY_FLOUNDER:
        case CHIP_VANGOGH:
        case CHIP_DIMGREY_CAVEFISH:
+       case CHIP_BEIGE_GOBY:
                break;
        default:
                break;
        case CHIP_DIMGREY_CAVEFISH:
                chip_name = "dimgrey_cavefish";
                break;
+       case CHIP_BEIGE_GOBY:
+               chip_name = "beige_goby";
+               break;
        default:
                BUG();
        }
                adev->sdma.num_instances = 2;
                break;
        case CHIP_VANGOGH:
+       case CHIP_BEIGE_GOBY:
                adev->sdma.num_instances = 1;
                break;
        default:
        case CHIP_NAVY_FLOUNDER:
        case CHIP_VANGOGH:
        case CHIP_DIMGREY_CAVEFISH:
+       case CHIP_BEIGE_GOBY:
                sdma_v5_2_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE);
                sdma_v5_2_update_medium_grain_light_sleep(adev,