arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588

The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device
tree nodes for them.

Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-7-a4f340a7f0cf@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 23a41c151c5deb6e6e3f9410771a6bb593c20609..e2500e31c434a8d01ece1f2b24815d4cc8f8bc8b 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -621,6 +621,16 @@
                reg = <0x0 0xfd5b0000 0x0 0x1000>;
        };
 
+       csidphy0_grf: syscon@fd5b4000 {
+               compatible = "rockchip,rk3588-csidphy-grf", "syscon";
+               reg = <0x0 0xfd5b4000 0x0 0x1000>;
+       };
+
+       csidphy1_grf: syscon@fd5b5000 {
+               compatible = "rockchip,rk3588-csidphy-grf", "syscon";
+               reg = <0x0 0xfd5b5000 0x0 0x1000>;
+       };
+
        pipe_phy0_grf: syscon@fd5bc000 {
                compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
                reg = <0x0 0xfd5bc000 0x0 0x100>;
@@ -3176,6 +3186,30 @@
                status = "disabled";
        };
 
+       csi_dphy0: phy@fedc0000 {
+               compatible = "rockchip,rk3588-csi-dphy";
+               reg = <0x0 0xfedc0000 0x0 0x8000>;
+               clocks = <&cru PCLK_CSIPHY0>;
+               clock-names = "pclk";
+               #phy-cells = <0>;
+               resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
+               reset-names = "apb", "phy";
+               rockchip,grf = <&csidphy0_grf>;
+               status = "disabled";
+       };
+
+       csi_dphy1: phy@fedc8000 {
+               compatible = "rockchip,rk3588-csi-dphy";
+               reg = <0x0 0xfedc8000 0x0 0x8000>;
+               clocks = <&cru PCLK_CSIPHY1>;
+               clock-names = "pclk";
+               #phy-cells = <0>;
+               resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>;
+               reset-names = "apb", "phy";
+               rockchip,grf = <&csidphy1_grf>;
+               status = "disabled";
+       };
+
        combphy0_ps: phy@fee00000 {
                compatible = "rockchip,rk3588-naneng-combphy";
                reg = <0x0 0xfee00000 0x0 0x100>;