mtd: rawnand: qcom: fix broken config in qcom_param_page_type_exec

Fix broken config in qcom_param_page_type_exec caused by copy-paste error
from commit 0c08080fd71c ("mtd: rawnand: qcom: use FIELD_PREP and GENMASK")

In qcom_param_page_type_exec the value needs to be set to
nandc->regs->cfg0 instead of host->cfg0. This wrong configuration caused
the Qcom NANDC driver to malfunction on any device that makes use of it
(IPQ806x, IPQ40xx, IPQ807x, IPQ60xx) with the following error:

[    0.885369] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xaa
[    0.885909] nand: Micron NAND 256MiB 1,8V 8-bit
[    0.892499] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
[    0.896823] nand: ECC (step, strength) = (512, 8) does not fit in OOB
[    0.896836] qcom-nandc 79b0000.nand-controller: No valid ECC settings possible
[    0.910996] bam-dma-engine 7984000.dma-controller: Cannot free busy channel
[    0.918070] qcom-nandc: probe of 79b0000.nand-controller failed with error -28

Restore original configuration fix the problem and makes the driver work
again.

Also restore the wrongly dropped cpu_to_le32 to correctly support BE
systems.

Cc: stable@vger.kernel.org
Fixes: 0c08080fd71c ("mtd: rawnand: qcom: use FIELD_PREP and GENMASK")
Tested-by: Robert Marko <robimarko@gmail.com> # IPQ8074 and IPQ6018
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index d2d2aeee42a7e00dbbde260e7d6818d4af860ea2..6720b547892ba80d653fc2f2e061cb2748830085 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -1881,18 +1881,18 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
        nandc->regs->addr0 = 0;
        nandc->regs->addr1 = 0;
 
-       host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
-                    FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
-                    FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
-                    FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
-
-       host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
-                    FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
-                    FIELD_PREP(CS_ACTIVE_BSY, 0) |
-                    FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
-                    FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
-                    FIELD_PREP(WIDE_FLASH, 0) |
-                    FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
+       nandc->regs->cfg0 = cpu_to_le32(FIELD_PREP(CW_PER_PAGE_MASK, 0) |
+                                       FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
+                                       FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
+                                       FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0));
+
+       nandc->regs->cfg1 = cpu_to_le32(FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
+                                       FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
+                                       FIELD_PREP(CS_ACTIVE_BSY, 0) |
+                                       FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
+                                       FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
+                                       FIELD_PREP(WIDE_FLASH, 0) |
+                                       FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1));
 
        if (!nandc->props->qpic_version2)
                nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);