#define        MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 #define        MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
 /* Allocate the controller structure and setup the linux irq descs
  * for the range if interrupts passed in. No HW initialization is
  * actually performed.
 
        .xlate = mpic_host_xlate,
 };
 
+static u32 fsl_mpic_get_version(struct mpic *mpic)
+{
+       u32 brr1;
+
+       if (!(mpic->flags & MPIC_FSL))
+               return 0;
+
+       brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
+                       MPIC_FSL_BRR1);
+
+       return brr1 & MPIC_FSL_BRR1_VER;
+}
+
 /*
  * Exported functions
  */
 
+u32 fsl_mpic_primary_get_version(void)
+{
+       struct mpic *mpic = mpic_primary;
+
+       if (mpic)
+               return fsl_mpic_get_version(mpic);
+
+       return 0;
+}
+
 struct mpic * __init mpic_alloc(struct device_node *node,
                                phys_addr_t phys_addr,
                                unsigned int flags,
        mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
 
        if (mpic->flags & MPIC_FSL) {
-               u32 brr1;
                int ret;
 
                /*
                mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
                         MPIC_CPU_THISBASE, 0x1000);
 
-               brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
-                               MPIC_FSL_BRR1);
-               fsl_version = brr1 & MPIC_FSL_BRR1_VER;
+               fsl_version = fsl_mpic_get_version(mpic);
 
                /* Error interrupt mask register (EIMR) is required for
                 * handling individual device error interrupts. EIMR
        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 
        if (mpic->flags & MPIC_FSL) {
-               u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
-                                     MPIC_FSL_BRR1);
-               u32 version = brr1 & MPIC_FSL_BRR1_VER;
+               u32 version = fsl_mpic_get_version(mpic);
 
                /*
                 * Timer group B is present at the latest in MPIC 3.1 (e.g.