drm/xe/xe2: Add Wa_15015404425

Wa_15015404425 asks us to perform four "dummy" writes to a
non-existent register offset before every real register read.
Although the specific offset of the writes doesn't directly
matter, the workaround suggests offset 0x130030 as a good target
so that these writes will be easy to recognize and filter out in
debugging traces.

V5(MattR):
  - Avoid negating an equality comparison
V4(MattR):
  - Use writel and remove xe_reg usage
V3(MattR):
  - Define dummy reg local to function
  - Avoid tracing dummy writes
  - Update commit message
V2:
  - Add WA to 8/16/32bit reads also - MattR
  - Corrected dummy reg address - MattR
  - Use for loop to avoid mental pause - JaniN

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240709155606.2998941-1-tejas.upadhyay@intel.com

diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index f92faad4b96d3c9aeaf4165c9c3bf630e5a51c0c..cf622d07e19069dc04a7c973f853ef9c00d974c4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -121,12 +121,29 @@ int xe_mmio_init(struct xe_device *xe)
        return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
 }
 
+static void mmio_flush_pending_writes(struct xe_gt *gt)
+{
+#define DUMMY_REG_OFFSET       0x130030
+       struct xe_tile *tile = gt_to_tile(gt);
+       int i;
+
+       if (tile->xe->info.platform != XE_LUNARLAKE)
+               return;
+
+       /* 4 dummy writes */
+       for (i = 0; i < 4; i++)
+               writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
+}
+
 u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
 {
        struct xe_tile *tile = gt_to_tile(gt);
        u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
        u8 val;
 
+       /* Wa_15015404425 */
+       mmio_flush_pending_writes(gt);
+
        val = readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
        trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
 
@@ -139,6 +156,9 @@ u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)
        u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
        u16 val;
 
+       /* Wa_15015404425 */
+       mmio_flush_pending_writes(gt);
+
        val = readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
        trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
 
@@ -160,6 +180,9 @@ u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
        u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
        u32 val;
 
+       /* Wa_15015404425 */
+       mmio_flush_pending_writes(gt);
+
        if (!reg.vf && IS_SRIOV_VF(gt_to_xe(gt)))
                val = xe_gt_sriov_vf_read32(gt, reg);
        else