Revert "drm/bridge: tc358767: Set default CLRSIPO count"

This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.

With clock improvements in place, this seems to be no longer
necessary. Set the CLRSIPO to default setting recommended by
manufacturer.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240625120334.145320-5-marex@denx.de

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 610df536a6edf0a6047d4bfa09a35a0c9dc1973e..b8b7a227addfb32e30f12cbb5316cedeac1c9332 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1356,10 +1356,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc)
        u32 value;
        int ret;
 
-       regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
-       regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
-       regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
-       regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
+       regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
+       regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
+       regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
+       regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
        regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
        regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
        regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);