{
        struct radeon_ring *ring = &rdev->ring[fence->ring];
        u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+
        /* write the fence */
        radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
        radeon_ring_write(ring, addr & 0xfffffffc);
        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
-       radeon_ring_write(ring, fence->seq);
+       radeon_ring_write(ring, lower_32_bits(fence->seq));
        /* generate an interrupt */
        radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
 }
 
        int r;
 
        radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
-       if (rdev->wb.use_event) {
+       if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
                rdev->fence_drv[ring].scratch_reg = 0;
                index = R600_WB_EVENT_OFFSET + ring * 4;
        } else {