drm/i915/reg: fix PCH transcoder timing indentation

Adhere to the style described at the top of i915_reg.h.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f56e48a927692cec382e292602e0fa68e37f3b93.1725974820.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f09145b979128eb07d1ec46aea3ac085f188875..1eede96a5415b8b10a68dc45c0e0af38da3e8b38 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3292,13 +3292,13 @@
 
 #define HSW_STEREO_3D_CTL(dev_priv, trans)     _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
 
-#define _PCH_TRANS_HTOTAL_B          0xe1000
-#define _PCH_TRANS_HBLANK_B          0xe1004
-#define _PCH_TRANS_HSYNC_B           0xe1008
-#define _PCH_TRANS_VTOTAL_B          0xe100c
-#define _PCH_TRANS_VBLANK_B          0xe1010
-#define _PCH_TRANS_VSYNC_B           0xe1014
-#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
+#define _PCH_TRANS_HTOTAL_B            0xe1000
+#define _PCH_TRANS_HBLANK_B            0xe1004
+#define _PCH_TRANS_HSYNC_B             0xe1008
+#define _PCH_TRANS_VTOTAL_B            0xe100c
+#define _PCH_TRANS_VBLANK_B            0xe1010
+#define _PCH_TRANS_VSYNC_B             0xe1014
+#define _PCH_TRANS_VSYNCSHIFT_B                0xe1028
 
 #define PCH_TRANS_HTOTAL(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
 #define PCH_TRANS_HBLANK(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)