{
        struct intel_uncore *uncore = &dev_priv->uncore;
 
-       u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
+       u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
+               GEN8_PIPE_CDCLK_CRC_DONE;
        u32 de_pipe_enables;
        u32 de_port_masked = GEN8_AUX_CHANNEL_A;
        u32 de_port_enables;
                de_misc_masked |= GEN8_DE_MISC_GSE;
 
        if (INTEL_GEN(dev_priv) >= 9) {
-               de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
                de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
                                  GEN9_AUX_CHANNEL_D;
                if (IS_GEN9_LP(dev_priv))
                        de_port_masked |= BXT_DE_PORT_GMBUS;
-       } else {
-               de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
        }
 
        if (INTEL_GEN(dev_priv) >= 11)