KVM: arm64: PMU: Restore the host's PMUSERENR_EL0

Restore the host's PMUSERENR_EL0 value instead of clearing it,
before returning back to userspace, as the host's EL0 might have
a direct access to PMU registers (some bits of PMUSERENR_EL0 for
might not be zero for the host EL0).

Fixes: 83a7a4d643d3 ("arm64: perf: Enable PMU counter userspace access for perf event")
Signed-off-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230603025035.3781797-2-reijiw@google.com

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 5c15c58f90ccebb1afe2c364a5fec23559dfad03..0dcb8f7620d1a74a6fbcd3f1c8002735ca176b84 100644 (file)
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -82,7 +82,12 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
         * EL1 instead of being trapped to EL2.
         */
        if (kvm_arm_support_pmu_v3()) {
+               struct kvm_cpu_context *hctxt;
+
                write_sysreg(0, pmselr_el0);
+
+               hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
+               ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
                write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
        }
 
@@ -106,8 +111,12 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
        write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
 
        write_sysreg(0, hstr_el2);
-       if (kvm_arm_support_pmu_v3())
-               write_sysreg(0, pmuserenr_el0);
+       if (kvm_arm_support_pmu_v3()) {
+               struct kvm_cpu_context *hctxt;
+
+               hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
+               write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
+       }
 
        if (cpus_have_final_cap(ARM64_SME)) {
                sysreg_clear_set_s(SYS_HFGRTR_EL2, 0,