arm64: dts: freescale: imx8mm-phyboard-polis: Add TPM node

Add TPM node for phyBOARD-Polis i.MX 8M Mini which has the Infineon-SLB
9670 TPM2.0 module populated.

Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index 03e7679217b24d9f09381a437fffdfabf8d167a9..cfb811091b7797cb31b119a330cd79997a8d04d0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@ -140,6 +140,27 @@
        };
 };
 
+/* TPM */
+&ecspi2 {
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       fsl,spi-num-chipselects = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       tpm: tpm@0 {
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+               interrupt-parent = <&gpio2>;
+               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpm>;
+               reg = <0>;
+               spi-max-frequency = <43000000>;
+       };
+};
+
 &gpio1 {
        gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
                "", "", "", "RESET_ETHPHY",
@@ -333,6 +354,15 @@
                >;
        };
 
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x80
+                       MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x80
+                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x80
+                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x00
+               >;
+       };
+
        pinctrl_fan: fan0grp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8        0x16
@@ -368,6 +398,12 @@
                >;
        };
 
+       pinctrl_tpm: tpmgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11      0x140
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX      0x00