udelay(300);
 }
 
+static void b43_radio_2059_init_pre(struct b43_wldev *dev)
+{
+       b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);
+       b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_FORCE);
+       b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_FORCE);
+       b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);
+}
+
 static void b43_radio_2059_init(struct b43_wldev *dev)
 {
        const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
        };
        u16 i, j;
 
+       /* Prepare (reset?) radio */
+       b43_radio_2059_init_pre(dev);
+
        b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
        b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
 
        if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
                b43err(dev->wl, "MAC not suspended\n");
 
-       /* In the following PHY ops we copy wl's dummy behaviour.
-        * TODO: Find out if reads (currently hidden in masks/masksets) are
-        * needed and replace following ops with just writes or w&r.
-        * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
-        * cause delayed (!) machine lock up. */
        if (blocked) {
-               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
+               b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD,
+                            ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);
        } else {
-               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
-               b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
-               b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
-               b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
-
                if (dev->phy.radio_ver == 0x2059)
                        b43_radio_2059_init(dev);
                else
 
 #define B43_PHY_HT_RF_SEQ_STATUS               B43_PHY_EXTG(0x004)
 /* Values for the status are the same as for the trigger */
 
-#define B43_PHY_HT_RF_CTL1                     B43_PHY_EXTG(0x010)
+#define B43_PHY_HT_RF_CTL_CMD                  0x810
+#define  B43_PHY_HT_RF_CTL_CMD_FORCE           0x0001
+#define  B43_PHY_HT_RF_CTL_CMD_CHIP0_PU                0x0002
 
 #define B43_PHY_HT_RF_CTL_INT_C1               B43_PHY_EXTG(0x04c)
 #define B43_PHY_HT_RF_CTL_INT_C2               B43_PHY_EXTG(0x06c)