arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003

The pre_ttbr0_update_workaround hook is called prior to context-switching
TTBR0 because Falkor erratum E1003 can cause TLB allocation with the wrong
ASID if both the ASID and the base address of the TTBR are updated at
the same time.

With the ASID sitting safely in TTBR1, we no longer update things
atomically, so we can remove the pre_ttbr0_update_workaround macro as
it's no longer required. The erratum infrastructure and documentation
is left around for #E1003, as it will be required by the entry
trampoline code in a future patch.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index aef72d886677758c76d6b932c863893df7c67b53..e1fa5db858b7f6ea09a7cea75a80ca33fb195ec9 100644 (file)
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -26,7 +26,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/cpufeature.h>
 #include <asm/debug-monitors.h>
-#include <asm/mmu_context.h>
 #include <asm/page.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/ptrace.h>
@@ -478,27 +477,6 @@ alternative_endif
        .endm
 
 /*
- * Errata workaround prior to TTBR0_EL1 update
- *
- *     val:    TTBR value with new BADDR, preserved
- *     tmp0:   temporary register, clobbered
- *     tmp1:   other temporary register, clobbered
- */
-       .macro  pre_ttbr0_update_workaround, val, tmp0, tmp1
-#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
-alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
-       mrs     \tmp0, ttbr0_el1
-       mov     \tmp1, #FALKOR_RESERVED_ASID
-       bfi     \tmp0, \tmp1, #48, #16          // reserved ASID + old BADDR
-       msr     ttbr0_el1, \tmp0
-       isb
-       bfi     \tmp0, \val, #0, #48            // reserved ASID + new BADDR
-       msr     ttbr0_el1, \tmp0
-       isb
-alternative_else_nop_endif
-#endif
-       .endm
-
 /*
  * Errata workaround post TTBR0_EL1 update.
  */

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index aa39c126c0d08a312e8233013177399e29d958a8..da29766a181ca71740686e65fca72b975f377b3e 100644 (file)
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -19,8 +19,6 @@
 #ifndef __ASM_MMU_CONTEXT_H
 #define __ASM_MMU_CONTEXT_H
 
-#define FALKOR_RESERVED_ASID   1
-
 #ifndef __ASSEMBLY__
 
 #include <linux/compiler.h>

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 6f4017046323f874e832cb07f5863283877179ba..78a2dc596fee13377b9e68504b79d9c22620b2d7 100644 (file)
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -79,13 +79,6 @@ void verify_cpu_asid_bits(void)
        }
 }
 
-static void set_reserved_asid_bits(void)
-{
-       if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_1003) &&
-           cpus_have_const_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003))
-               __set_bit(FALKOR_RESERVED_ASID, asid_map);
-}
-
 static void flush_context(unsigned int cpu)
 {
        int i;
@@ -94,8 +87,6 @@ static void flush_context(unsigned int cpu)
        /* Update the list of reserved ASIDs and the ASID bitmap. */
        bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
 
-       set_reserved_asid_bits();
-
        for_each_possible_cpu(i) {
                asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
                /*
@@ -254,8 +245,6 @@ static int asids_init(void)
                panic("Failed to allocate bitmap for %lu ASIDs\n",
                      NUM_USER_ASIDS);
 
-       set_reserved_asid_bits();
-
        pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
        return 0;
 }

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index a8a64898a2aac7db77a8d42d30bfaa8174d29124..f2ff0837577c0483adcf684227bceb2f364d63d1 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -138,7 +138,6 @@ ENDPROC(cpu_do_resume)
  *     - pgd_phys - physical address of new TTB
  */
 ENTRY(cpu_do_switch_mm)
-       pre_ttbr0_update_workaround x0, x2, x3
        mrs     x2, ttbr1_el1
        mmid    x1, x1                          // get mm->context.id
        bfi     x2, x1, #48, #16                // set the ASID