Merge tag 'x86-cleanups-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel...

Pull x86 cleanups from Ingo Molnar:
 "Miscellaneous x86 cleanups and typo fixes, and also the removal of
  the 'disablelapic' boot parameter"

* tag 'x86-cleanups-2025-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/ioapic: Remove a stray tab in the IO-APIC type string
  x86/cpufeatures: Remove "AMD" from the comments to the AMD-specific leaf
  Documentation/kernel-parameters: Fix a typo in kvm.enable_virt_at_load text
  x86/cpu: Fix typo in x86_match_cpu()'s doc
  x86/apic: Remove "disablelapic" cmdline option
  Documentation: Merge x86-specific boot options doc into kernel-parameters.txt
  x86/ioremap: Remove unused size parameter in remapping functions
  x86/ioremap: Simplify setup_data mapping variants
  x86/boot/compressed: Remove unused header includes from kaslr.c

diff --cc arch/x86/include/asm/cpufeatures.h
index 4cf44002336c9e4f828395e7e69d1988475786f6,09e1e54676f400edf7d58a0e10cab7fb08ac05f6..508c0dad116bc42fbdf1cffee2758f824838a7c3
--- 1/arch/x86/include/asm/cpufeatures.h
--- 2/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -443,18 -443,15 +443,18 @@@
  #define X86_FEATURE_SPEC_CTRL_SSBD    (18*32+31) /* Speculative Store Bypass Disable */
  
  /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
- #define X86_FEATURE_SME                       (19*32+ 0) /* "sme" AMD Secure Memory Encryption */
- #define X86_FEATURE_SEV                       (19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */
+ #define X86_FEATURE_SME                       (19*32+ 0) /* "sme" Secure Memory Encryption */
+ #define X86_FEATURE_SEV                       (19*32+ 1) /* "sev" Secure Encrypted Virtualization */
  #define X86_FEATURE_VM_PAGE_FLUSH     (19*32+ 2) /* VM Page Flush MSR is supported */
- #define X86_FEATURE_SEV_ES            (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */
- #define X86_FEATURE_SEV_SNP           (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */
+ #define X86_FEATURE_SEV_ES            (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */
+ #define X86_FEATURE_SEV_SNP           (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */
  #define X86_FEATURE_V_TSC_AUX         (19*32+ 9) /* Virtual TSC_AUX */
- #define X86_FEATURE_SME_COHERENT      (19*32+10) /* AMD hardware-enforced cache coherency */
- #define X86_FEATURE_DEBUG_SWAP                (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */
+ #define X86_FEATURE_SME_COHERENT      (19*32+10) /* hardware-enforced cache coherency */
+ #define X86_FEATURE_DEBUG_SWAP                (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
 +#define X86_FEATURE_RMPREAD           (19*32+21) /* RMPREAD instruction */
 +#define X86_FEATURE_SEGMENTED_RMP     (19*32+23) /* Segmented RMP support */
  #define X86_FEATURE_SVSM              (19*32+28) /* "svsm" SVSM present */
 +#define X86_FEATURE_HV_INUSE_WR_ALLOWED       (19*32+30) /* Allow Write to in-use hypervisor-owned pages */
  
  /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
  #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */

diff --cc arch/x86/kernel/apic/apic.c
Simple merge

diff --cc arch/x86/kernel/cpu/match.c
Simple merge