#7: - Miscellanous W7O specific stuff.
- W7O support for other boot ROMs.
- W7O failsafe boot mechanism (for VxWorks upgrades).
- W7O SPD support.
- W7O VPD support routines.
- Code cleanup.
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ERRORS_H_
+#define _ERRORS_H_
+
+#define ERR_FF -1 /* led test value(2) */
+#define ERR_00 0x0000 /* led test value(2) */
+#define ERR_LED 0x01 /* led test failed (1)(3)(4) */
+#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */
+#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */
+#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */
+#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */
+#define ERR_ADDG 0x08 /* start Address ghosting test (13) */
+#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */
+#define ERR_POST1 0x0a /* post1 tests complete */
+#define ERR_TMP1 0x0b /* */
+#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */
+#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */
+#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */
+#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */
+#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */
+#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */
+#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */
+#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */
+#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */
+#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */
+#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */
+#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */
+#define ERR_RTCG 0x18 /* start RTC test */
+#define ERR_RTCBAT 0x19 /* RTC battery failure */
+#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */
+#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */
+#define ERR_FPGAG 0x20 /* fault during FPGA programming */
+#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */
+#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */
+#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */
+#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */
+#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */
+#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */
+#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */
+#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */
+#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */
+#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */
+#define ERR_TempG 0x2b /* start temp sensor tests */
+#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */
+#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */
+#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */
+#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */
+#define ERR_lm75r 0x30 /* temp sensor read failure */
+#define ERR_lm75w 0x31 /* temp sensor write failure */
+
+
+#define ERR_POSTOK 0x55 /* PANIC: psych... OK */
+
+#if !defined(__ASSEMBLY__)
+extern void log_stat(int errcode);
+extern void log_warn(int errcode);
+extern void log_err(int errcode);
+#endif
+
+/*
+Debugging suggestions:
+(1) periferal data bus shorted or crossed
+(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
+(3) check p_we, p_r/w, p_oe, p_rdy lines.
+(4) check LED buffers
+(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
+(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
+(7) check SDRAM control lines and clocks
+(8) check decoupling caps, replace LSW SDRAM
+(9) check decoupling caps, replace MSW SDRAM
+(10)
+(11)
+(12)
+(13) SDRAM address shorted or unconnected, check sdram caps
+*/
+#endif /* _ERRORS_H_ */
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wave 7 Optics, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <config.h>
+#include <command.h>
+#include <cmd_elf.h>
+
+/*
+ * FIXME: Add code to test image and it's header.
+ */
+static int
+image_check(ulong addr)
+{
+ return valid_elf_image(addr);
+}
+
+void
+init_fsboot(void)
+{
+ char *envp;
+ ulong loadaddr;
+ ulong testaddr;
+ ulong alt_loadaddr;
+ char buf[9];
+
+ /*
+ * Get test image address
+ */
+ if ((envp = getenv("testaddr")) != NULL)
+ testaddr = simple_strtoul(envp, NULL, 16);
+ else
+ testaddr = -1;
+
+ /*
+ * Are we going to test boot and image?
+ */
+ if ((testaddr != -1) && image_check(testaddr)) {
+
+ /* Set alt_loadaddr */
+ alt_loadaddr = testaddr;
+ sprintf(buf, "%lX", alt_loadaddr);
+ setenv("alt_loadaddr", buf);
+
+ /* Clear test_addr */
+ setenv("testaddr", NULL);
+
+ /*
+ * Save current environment with alt_loadaddr,
+ * and cleared testaddr.
+ */
+ saveenv();
+
+ /*
+ * Setup temporary loadaddr to alt_loadaddr
+ * XXX - DO NOT SAVE ENVIRONMENT!
+ */
+ loadaddr = alt_loadaddr;
+ sprintf(buf, "%lX", loadaddr);
+ setenv("loadaddr", buf);
+
+ } else { /* Normal boot */
+ setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */
+ setenv("testaddr", NULL); /* Clear testaddr */
+ saveenv();
+ }
+
+ return;
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
+ * and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <config.h>
+#include <rtc.h>
+#include "errors.h"
+#include "dtt.h"
+
+#if defined(CONFIG_RTC_M48T35A)
+void rtctest(void)
+{
+ volatile uchar *tchar = (uchar*)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9);
+ struct rtc_time tmp;
+
+ /* set up led code for RTC tests */
+ log_stat(ERR_RTCG);
+
+ /*
+ * Do RTC battery test. The first write after power up
+ * fails if battery is low.
+ */
+ *tchar = 0xaa;
+ if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT);
+ *tchar = 0x55; /* Reset test address */
+
+ /*
+ * Now lets check the validity of the values in the RTC.
+ */
+ rtc_get(&tmp);
+ if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) |
+ (tmp.tm_min < 0) | (tmp.tm_min > 59) |
+ (tmp.tm_hour < 0) | (tmp.tm_hour > 23) |
+ (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) |
+ (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) |
+ (tmp.tm_year < 2000) | (tmp.tm_year > 2500) |
+ (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) {
+ log_warn(ERR_RTCTIM);
+ rtc_reset();
+ }
+
+ /*
+ * Now lets do a check to see if the NV RAM is there.
+ */
+ *tchar = 0xaa;
+ if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL);
+ *tchar = 0x55; /* Reset test address */
+
+} /* rtctest() */
+#endif /* CONFIG_RTC_M48T35A */
+
+
+#ifdef CONFIG_DTT_LM75
+int dtt_test(int sensor)
+{
+ short temp, trip, hyst;
+
+ /* get values */
+ temp = dtt_read(sensor, DTT_READ_TEMP) / 256;
+ trip = dtt_read(sensor, DTT_TEMP_SET) / 256;
+ hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
+
+ /* check values */
+ if ((hyst != (CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS)) ||
+ (trip != CFG_DTT_MAX_TEMP) ||
+ (temp < CFG_DTT_LOW_TEMP) || (temp > CFG_DTT_MAX_TEMP))
+ return 1;
+
+ return 0;
+} /* dtt_test() */
+#endif /* CONFIG_DTT_LM75 */
+
+/*****************************************/
+
+void post2(void)
+{
+#if defined(CONFIG_RTC_M48T35A)
+ rtctest();
+#endif /* CONFIG_RTC_M48T35A */
+
+#ifdef CONFIG_DTT_LM75
+ log_stat(ERR_TempG);
+ if(dtt_test(2) != 0) log_warn(ERR_Ttest0);
+ if(dtt_test(4) != 0) log_warn(ERR_Ttest1);
+#endif /* CONFIG_DTT_LM75 */
+} /* post2() */
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * W7O board level hardware watchdog.
+ */
+#include <ppcboot.h>
+#include <config.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+void hw_watchdog_reset(void)
+{
+ volatile ushort *hwd = (ushort *)(CFG_W7O_EBC_PB7CR & 0xfff00000);
+
+ /*
+ * Read the LMG's hwd register and toggle the
+ * watchdog bit to reset it. On the LMC, just
+ * reading it is enough, but toggling the bit
+ * doen't hurt either.
+ */
+ *hwd = *hwd ^ 0x8000;
+
+} /* hw_watchdog_reset() */
+
+#endif /* CONFIG_HW_WATCHDOG */
+
projects / users / rw / ppcboot.git / commitdiff