drm/i915/mtl: Update MBUS_DBOX credits

Display version 14 platforms have different credits values
compared to ADL-P. Update the credits based on pipe usage.

v2: Simplify DBOX BW Credit definition(MattR)
v3:
 - Simplify only pipe per dbuf bank check(MattR)
 - Skip modeset check to handle the case when a new pipe within
   dbuf bank gets added/removed.(MattR)

Bspec: 49213

Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220913183341.908028-5-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 617a1f2d01ea9b57cd6cfed6fcf63984401d63ab..01b0932757ed7df2b7f3383fff61ac562f0ccea4 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3412,6 +3412,25 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
                                new_dbuf_state->enabled_slices);
 }
 
+static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
+{
+       switch (pipe) {
+       case PIPE_A:
+               return !(active_pipes & BIT(PIPE_D));
+       case PIPE_D:
+               return !(active_pipes & BIT(PIPE_A));
+       case PIPE_B:
+               return !(active_pipes & BIT(PIPE_C));
+       case PIPE_C:
+               return !(active_pipes & BIT(PIPE_B));
+       default: /* to suppress compiler warning */
+               MISSING_CASE(pipe);
+               break;
+       }
+
+       return false;
+}
+
 void intel_mbus_dbox_update(struct intel_atomic_state *state)
 {
        struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -3431,20 +3450,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
             new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
                return;
 
+       if (DISPLAY_VER(i915) >= 14)
+               val |= MBUS_DBOX_I_CREDIT(2);
+
        if (DISPLAY_VER(i915) >= 12) {
                val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
                val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
                val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
        }
 
-       /* Wa_22010947358:adl-p */
-       if (IS_ALDERLAKE_P(i915))
+       if (DISPLAY_VER(i915) >= 14)
+               val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
+                                                    MBUS_DBOX_A_CREDIT(8);
+       else if (IS_ALDERLAKE_P(i915))
+               /* Wa_22010947358:adl-p */
                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
                                                     MBUS_DBOX_A_CREDIT(4);
        else
                val |= MBUS_DBOX_A_CREDIT(2);
 
-       if (IS_ALDERLAKE_P(i915)) {
+       if (DISPLAY_VER(i915) >= 14) {
+               val |= MBUS_DBOX_B_CREDIT(0xA);
+       } else if (IS_ALDERLAKE_P(i915)) {
                val |= MBUS_DBOX_BW_CREDIT(2);
                val |= MBUS_DBOX_B_CREDIT(8);
        } else if (DISPLAY_VER(i915) >= 12) {
@@ -3456,11 +3483,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
        }
 
        for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-               if (!new_crtc_state->hw.active ||
-                   !intel_crtc_needs_modeset(new_crtc_state))
+               u32 pipe_val = val;
+
+               if (!new_crtc_state->hw.active)
                        continue;
 
-               intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val);
+               if (DISPLAY_VER(i915) >= 14) {
+                       if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
+                                                             new_dbuf_state->active_pipes))
+                               pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
+                       else
+                               pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
+               }
+
+               intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6756237f6162926e51f1c6ce236d383268479ee8..7c46a9fd34f2bf0686cf4d714388fe2572798766 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1125,8 +1125,12 @@
 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
 #define MBUS_DBOX_BW_CREDIT_MASK               REG_GENMASK(15, 14)
 #define MBUS_DBOX_BW_CREDIT(x)                 REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
+#define MBUS_DBOX_BW_4CREDITS_MTL              REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
+#define MBUS_DBOX_BW_8CREDITS_MTL              REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
 #define MBUS_DBOX_B_CREDIT_MASK                        REG_GENMASK(12, 8)
 #define MBUS_DBOX_B_CREDIT(x)                  REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
+#define MBUS_DBOX_I_CREDIT_MASK                        REG_GENMASK(7, 5)
+#define MBUS_DBOX_I_CREDIT(x)                  REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
 #define MBUS_DBOX_A_CREDIT_MASK                        REG_GENMASK(3, 0)
 #define MBUS_DBOX_A_CREDIT(x)                  REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)