MIPS: unaligned: Remove FP & MSA code when unsupported

When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so remove
support for floating point instructions from emulate_load_store_insn() &
emulate_load_store_microMIPS(). This code should not be needed & relies
upon access to FPU state in struct task_struct which will later be
removed.

Similarly & for the same reasons, when CONFIG_CPU_HAS_MSA=n remove
support for MSA instructions. Since MSA support depends upon FP support
this is implied when CONFIG_MIPS_FP_SUPPORT=n.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21020/
Cc: linux-mips@linux-mips.org

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 4c7de9f6373d7e4249e05903ed3d0f72fdd480ac..3850c563e5885f8825923070ebc0b0295f8febb1 100644 (file)
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -882,18 +882,12 @@ do {                                                        \
 static void emulate_load_store_insn(struct pt_regs *regs,
        void __user *addr, unsigned int __user *pc)
 {
+       unsigned long origpc, orig31, value;
        union mips_instruction insn;
-       unsigned long value;
-       unsigned int res, preempted;
-       unsigned long origpc;
-       unsigned long orig31;
-       void __user *fault_addr = NULL;
+       unsigned int res;
 #ifdef CONFIG_EVA
        mm_segment_t seg;
 #endif
-       union fpureg *fpr;
-       enum msa_2b_fmt df;
-       unsigned int wd;
        origpc = (unsigned long)pc;
        orig31 = regs->regs[31];
 
@@ -1212,11 +1206,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
                /* Cannot handle 64-bit instructions in 32-bit kernel */
                goto sigill;
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
+
        case lwc1_op:
        case ldc1_op:
        case swc1_op:
        case sdc1_op:
-       case cop1x_op:
+       case cop1x_op: {
+               void __user *fault_addr = NULL;
+
                die_if_kernel("Unaligned FP access in kernel code", regs);
                BUG_ON(!used_math());
 
@@ -1230,8 +1228,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
                if (res == 0)
                        break;
                return;
+       }
+#endif /* CONFIG_MIPS_FP_SUPPORT */
+
+#ifdef CONFIG_CPU_HAS_MSA
+
+       case msa_op: {
+               unsigned int wd, preempted;
+               enum msa_2b_fmt df;
+               union fpureg *fpr;
 
-       case msa_op:
                if (!cpu_has_msa)
                        goto sigill;
 
@@ -1308,6 +1314,8 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 
                compute_return_epc(regs);
                break;
+       }
+#endif /* CONFIG_CPU_HAS_MSA */
 
 #ifndef CONFIG_CPU_MIPSR6
        /*
@@ -1392,7 +1400,6 @@ static void emulate_load_store_microMIPS(struct pt_regs *regs,
        unsigned long origpc, contpc;
        union mips_instruction insn;
        struct mm_decoded_insn mminsn;
-       void __user *fault_addr = NULL;
 
        origpc = regs->cp0_epc;
        orig31 = regs->regs[31];
@@ -1708,6 +1715,7 @@ static void emulate_load_store_microMIPS(struct pt_regs *regs,
                /*  LL,SC,LLD,SCD are not serviced */
                goto sigbus;
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
        case mm_pool32f_op:
                switch (insn.mm_x_format.func) {
                case mm_lwxc1_func:
@@ -1722,7 +1730,9 @@ static void emulate_load_store_microMIPS(struct pt_regs *regs,
        case mm_ldc132_op:
        case mm_sdc132_op:
        case mm_lwc132_op:
-       case mm_swc132_op:
+       case mm_swc132_op: {
+               void __user *fault_addr = NULL;
+
 fpu_emul:
                /* roll back jump/branch */
                regs->cp0_epc = origpc;
@@ -1742,6 +1752,8 @@ fpu_emul:
                if (res == 0)
                        goto success;
                return;
+       }
+#endif /* CONFIG_MIPS_FP_SUPPORT */
 
        case mm_lh32_op:
                reg = insn.mm_i_format.rt;