In some circumstances the current implementation of the SPI memory
operations may occasionally fail even though they are executed in the
atomic context. This may happen if the system bus is relatively slow in
comparison to the SPI bus frequency, or there is a concurrent access to
it, which makes the MMIO-operations occasionally stalling before
push-pulling data from the DW APB SPI FIFOs. These two problems we've
discovered on the Baikal-T1 SoC. In order to fix them we have no choice
but to set an artificial limitation on the SPI bus speed.
Note currently this limitation will be only applicable for the memory
operations, since the standard SPI core interface is implemented with an
assumption that there is no problem with the automatic CS toggling.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20201007235511.4935-19-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
 
         * operation. Transmit-only mode is suitable for the rest of them.
         */
        cfg.dfs = 8;
-       cfg.freq = mem->spi->max_speed_hz;
+       cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq);
        if (op->data.dir == SPI_MEM_DATA_IN) {
                cfg.tmode = SPI_TMOD_EPROMREAD;
                cfg.ndf = op->data.nbytes;
                dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
                dws->mem_ops.supports_op = dw_spi_supports_mem_op;
                dws->mem_ops.exec_op = dw_spi_exec_mem_op;
+               if (!dws->max_mem_freq)
+                       dws->max_mem_freq = dws->max_freq;
        }
 }
 
 
        unsigned long           paddr;
        int                     irq;
        u32                     fifo_len;       /* depth of the FIFO buffer */
+       u32                     max_mem_freq;   /* max mem-ops bus freq */
        u32                     max_freq;       /* max bus freq supported */
 
        u32                     caps;           /* DW SPI capabilities */