*/
 
 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
-               uint32_t gfx_clock, PllSetting_t *current_gfxclk_level)
+               uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
+               uint32_t *acg_freq)
 {
        struct phm_ppt_v2_information *table_info =
                        (struct phm_ppt_v2_information *)(hwmgr->pptable);
                        cpu_to_le16(dividers.usPll_ss_slew_frac);
        current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
 
+       *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
+
        return 0;
 }
 
        for (i = 0; i < dpm_table->count; i++) {
                result = vega10_populate_single_gfx_level(hwmgr,
                                dpm_table->dpm_levels[i].value,
-                               &(pp_table->GfxclkLevel[i]));
+                               &(pp_table->GfxclkLevel[i]),
+                               &(pp_table->AcgFreqTable[i]));
                if (result)
                        return result;
        }
        while (i < NUM_GFXCLK_DPM_LEVELS) {
                result = vega10_populate_single_gfx_level(hwmgr,
                                dpm_table->dpm_levels[j].value,
-                               &(pp_table->GfxclkLevel[i]));
+                               &(pp_table->GfxclkLevel[i]),
+                               &(pp_table->AcgFreqTable[i]));
                if (result)
                        return result;
                i++;
 
   uint8_t      AcgEnable[NUM_GFXCLK_DPM_LEVELS];
   GbVdroopTable_t AcgBtcGbVdroopTable;
   QuadraticInt_t  AcgAvfsGb;
-  uint32_t     Reserved[4];
+
+  /* ACG Frequency Table, in Mhz */
+  uint32_t     AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];
 
   /* Padding - ignore */
-  uint32_t     MmHubPadding[7]; /* SMU internal use */
+  uint32_t     MmHubPadding[3]; /* SMU internal use */
 
 } PPTable_t;