#define XGMAC_CONFIG_GPSL              GENMASK(29, 16)
 #define XGMAC_CONFIG_GPSL_SHIFT                16
 #define XGMAC_CONFIG_S2KP              BIT(11)
+#define XGMAC_CONFIG_LM                        BIT(10)
 #define XGMAC_CONFIG_IPC               BIT(9)
 #define XGMAC_CONFIG_JE                        BIT(8)
 #define XGMAC_CONFIG_WD                        BIT(7)
 
        writel(value, ioaddr + XGMAC_PACKET_FILTER);
 }
 
+static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)
+{
+       u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
+
+       if (enable)
+               value |= XGMAC_CONFIG_LM;
+       else
+               value &= ~XGMAC_CONFIG_LM;
+
+       writel(value, ioaddr + XGMAC_RX_CONFIG);
+}
+
 const struct stmmac_ops dwxgmac210_ops = {
        .core_init = dwxgmac2_core_init,
        .set_mac = dwxgmac2_set_mac,
        .pcs_get_adv_lp = NULL,
        .debug = NULL,
        .set_filter = dwxgmac2_set_filter,
+       .set_mac_loopback = dwxgmac2_set_mac_loopback,
 };
 
 int dwxgmac2_setup(struct stmmac_priv *priv)