The load instruction used within arch_load_niai4() has a short displacement
and index register. Therefore use the R constraint to reflect this.
The used Q constraint does consider an index register.
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
asm_inline volatile(
ALTERNATIVE("nop", ".insn rre,0xb2fa0000,4,0", ALT_FACILITY(49)) /* NIAI 4 */
" l %[owner],%[lock]\n"
- : [owner] "=d" (owner) : [lock] "Q" (*lock) : "memory");
+ : [owner] "=d" (owner) : [lock] "R" (*lock) : "memory");
return owner;
}