drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement

Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
and then configures the Pixel PLL register.

This is a preparatory patch for further rework, where tc_pxl_pll_calc()
will also be used to find out the exact clock frequency generated by the
Pixel PLL. This frequency will be used as adjusted_mode clock frequency
and passed down the display pipeline to obtain exactly this frequency
on input into this bridge.

The precise input frequency that matches the Pixel PLL frequency is
important for this bridge, as if the frequencies do not match, the
bridge does suffer VFIFO overruns or underruns.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240625120334.145320-1-marex@denx.de

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 6bda26ca6b917e27b6ce81179d5b8a0c9c14a321..a2d073e4856f319556d859c75a03156700548aa3 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -585,9 +585,9 @@ static u32 div64_round_up(u64 v, u32 d)
        return div_u64(v + d - 1, d);
 }
 
-static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
+static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
+                          int *out_best_pixelclock, u32 *out_pxl_pllparam)
 {
-       int ret;
        int i_pre, best_pre = 1;
        int i_post, best_post = 1;
        int div, best_div = 1;
@@ -683,11 +683,6 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
        if (best_mul == 128)
                best_mul = 0;
 
-       /* Power up PLL and switch to bypass */
-       ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
-       if (ret)
-               return ret;
-
        pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
        pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
        pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
@@ -695,6 +690,29 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
        pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
        pxl_pllparam |= best_mul; /* Multiplier for PLL */
 
+       if (out_best_pixelclock)
+               *out_best_pixelclock = best_pixelclock;
+
+       if (out_pxl_pllparam)
+               *out_pxl_pllparam = pxl_pllparam;
+
+       return 0;
+}
+
+static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
+{
+       u32 pxl_pllparam = 0;
+       int ret;
+
+       ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam);
+       if (ret)
+               return ret;
+
+       /* Power up PLL and switch to bypass */
+       ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
+       if (ret)
+               return ret;
+
        ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
        if (ret)
                return ret;