MIPS: CPS: Use change_*, set_* & clear_* where appropriate

Make use of the new change_*, set_* & clear_* accessor functions for CPS
(CM, CPC & GIC) registers where doing so makes the code easier to read
or shortens it without adversely affecting readability.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17005/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index 91b861ebc907d793720faef0f783a2fe8113c806..497dbb1284380823caf2d6e845f0b1a3919a3379 100644 (file)
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -233,9 +233,7 @@ int mips_cm_probe(void)
        }
 
        /* set default target to memory */
-       base_reg &= ~CM_GCR_BASE_CMDEFTGT;
-       base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
-       write_gcr_base(base_reg);
+       change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
 
        /* disable CM regions */
        write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);

diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 777e0193e8ed3f35d012ebcb388c969d7b6233b1..5729d2c77461118c8e73b240d64e0a88e94469cd 100644 (file)
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -212,7 +212,7 @@ err_out:
 
 static void boot_core(unsigned int core, unsigned int vpe_id)
 {
-       u32 access, stat, seq_state;
+       u32 stat, seq_state;
        unsigned timeout;
 
        /* Select the appropriate core */
@@ -228,9 +228,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
        write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
 
        /* Ensure the core can access the GCRs */
-       access = read_gcr_access();
-       access |= 1 << core;
-       write_gcr_access(access);
+       set_gcr_access(1 << core);
 
        if (mips_cpc_present()) {
                /* Reset the core */

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 7f30397cb10d2ff19685ac5defe06a82a8ad1dca..cda878c0010baea31e324ee39095a887518386cc 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -69,28 +69,19 @@ static void mips_sc_prefetch_enable(void)
                pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN;
                write_gcr_l2_pft_control(pftctl);
 
-               pftctl = read_gcr_l2_pft_control_b();
-               pftctl |= CM_GCR_L2_PFT_CONTROL_B_PORTID;
-               pftctl |= CM_GCR_L2_PFT_CONTROL_B_CEN;
-               write_gcr_l2_pft_control_b(pftctl);
+               set_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
+                                        CM_GCR_L2_PFT_CONTROL_B_CEN);
        }
 }
 
 static void mips_sc_prefetch_disable(void)
 {
-       unsigned long pftctl;
-
        if (mips_cm_revision() < CM_REV_CM2_5)
                return;
 
-       pftctl = read_gcr_l2_pft_control();
-       pftctl &= ~CM_GCR_L2_PFT_CONTROL_PFTEN;
-       write_gcr_l2_pft_control(pftctl);
-
-       pftctl = read_gcr_l2_pft_control_b();
-       pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_PORTID;
-       pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_CEN;
-       write_gcr_l2_pft_control_b(pftctl);
+       clear_gcr_l2_pft_control(CM_GCR_L2_PFT_CONTROL_PFTEN);
+       clear_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
+                                  CM_GCR_L2_PFT_CONTROL_B_CEN);
 }
 
 static bool mips_sc_prefetch_is_enabled(void)