Judgement whether to add an sw ip according to the harvest info.
v2: fix indentation (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
        struct amdgpu_df                df;
 
        struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
+       uint32_t                        harvest_ip_mask;
        int                             num_ip_blocks;
        struct mutex    mn_lock;
        DECLARE_HASHTABLE(mn_hash, 7);
 
        if (!ip_block_version)
                return -EINVAL;
 
+       switch (ip_block_version->type) {
+       case AMD_IP_BLOCK_TYPE_VCN:
+               if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
+                       return 0;
+               break;
+       case AMD_IP_BLOCK_TYPE_JPEG:
+               if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
+                       return 0;
+               break;
+       default:
+               break;
+       }
+
        DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
                  ip_block_version->funcs->name);
 
        return amdgpu_device_asic_has_dc_support(adev->asic_type);
 }
 
-
 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
 {
        struct amdgpu_device *adev =
        adev->vm_manager.vm_pte_funcs = NULL;
        adev->vm_manager.vm_pte_num_scheds = 0;
        adev->gmc.gmc_funcs = NULL;
+       adev->harvest_ip_mask = 0x0;
        adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
        bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 
 
        return -EINVAL;
 }
 
+void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
+{
+       struct binary_header *bhdr;
+       struct harvest_table *harvest_info;
+       int i;
+
+       bhdr = (struct binary_header *)adev->mman.discovery_bin;
+       harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
+                       le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
+
+       for (i = 0; i < 32; i++) {
+               if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)
+                       break;
+
+               switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
+               case VCN_HWID:
+                       adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
+                       adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
+                       break;
+               case DMU_HWID:
+                       adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
+                       break;
+               default:
+                       break;
+               }
+       }
+}
+
 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
 
 
 void amdgpu_discovery_fini(struct amdgpu_device *adev);
 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
+void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
                                     int *major, int *minor, int *revision);
 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
 
                        goto legacy_init;
                }
 
+               amdgpu_discovery_harvest_ip(adev);
+
                return 0;
        }
 
                amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
                if (!amdgpu_sriov_vf(adev))
                        amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
-
                if (adev->enable_mes)
                        amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
                break;
                return -EINVAL;
        }
 
+       if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
+               adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
+                                   AMD_PG_SUPPORT_VCN_DPG |
+                                   AMD_PG_SUPPORT_JPEG);
+
        if (amdgpu_sriov_vf(adev)) {
                amdgpu_virt_init_setting(adev);
                xgpu_nv_mailbox_set_irq_funcs(adev);
 
        PP_GFX_DCS_MASK = 0x80000,
 };
 
+enum amd_harvest_ip_mask {
+    AMD_HARVEST_IP_VCN_MASK = 0x1,
+    AMD_HARVEST_IP_JPEG_MASK = 0x2,
+    AMD_HARVEST_IP_DMU_MASK = 0x4,
+};
+
 enum DC_FEATURE_MASK {
        DC_FBC_MASK = 0x1,
        DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,