*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
suit your needs */
/* first ethernet */
-#define CONFIG_ETHADDR 00:00:5B:00:6E:8A
+#define CONFIG_ETHADDR 00:00:5B:00:6E:8A
#define CONFIG_IPADDR 172.22.2.112
-#define CONFIG_SERVERIP 172.22.2.111
+#define CONFIG_SERVERIP 172.22.2.111
#define CONFIG_ENV_OVERWRITE
#define CONFIG_75x 1 /* This is a MPC75x */
#define CONFIG_BAB750 1 /* ...on an BAB750 board */
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#undef CONFIG_WATCHDOG
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp 1000000; " \
+ "bootp 1000000; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):eth0:none; "\
- "bootm"
+ "bootm"
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
+#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE | CFG_CMD_FDC)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE | CFG_CMD_FDC)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
/*
* choose between COM1 and COM2 as serial console
#define CONFIG_CONS_INDEX 1
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#undef CFG_MEMTEST
#endif
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_CPU_CLK 266000000
#define CFG_BUS_CLK 6600000
* Do NOT change the following table!!! Important mapping information!!
*/
#ifdef CFG_ADDRESS_MAP_A
-#define CFG_ISA_MEM 0xC0000000
-#define CFG_ISA_IO_BASE_ADDRESS 0x80000000
-#define CFG_ISA_IO CFG_ISA_IO_BASE_ADDRESS
-#define CFG_PCI_IO_BASE_ADDRESS 0x81000000
-#define CFG_PCI_IO CFG_PCI_IO_BASE_ADDRESS
+#define CFG_ISA_MEM 0xC0000000
+#define CFG_ISA_IO_BASE_ADDRESS 0x80000000
+#define CFG_ISA_IO CFG_ISA_IO_BASE_ADDRESS
+#define CFG_PCI_IO_BASE_ADDRESS 0x81000000
+#define CFG_PCI_IO CFG_PCI_IO_BASE_ADDRESS
#else
-#define CFG_ISA_MEM 0xFD000000
-#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
-#define CFG_ISA_IO CFG_ISA_IO_BASE_ADDRESS
-#define CFG_PCI_IO_BASE_ADDRESS 0xFE800000
-#define CFG_PCI_IO CFG_PCI_IO_BASE_ADDRESS
+#define CFG_ISA_MEM 0xFD000000
+#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
+#define CFG_ISA_IO CFG_ISA_IO_BASE_ADDRESS
+#define CFG_PCI_IO_BASE_ADDRESS 0xFE800000
+#define CFG_PCI_IO CFG_PCI_IO_BASE_ADDRESS
#endif
/*
* PCI stuff
*/
-#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO
-#define CONFIG_PCI_PNP /* pci plug-and-play */
+#define CONFIG_PCI_PNP /* pci plug-and-play */
/*
* Do NOT change the following table!!! Important mapping information!!
*/
#ifdef CFG_ADDRESS_MAP_A
-#define CFG_PCI_DRAM_OFFSET 0x80000000
+#define CFG_PCI_DRAM_OFFSET 0x80000000
#define CFG_60X_PCI_MEM_OFFSET 0xC0000000
#define CFG_60X_PCI_IO_OFFSET 0x80000000
#define CFG_MIN_PCI_MEMADDR1 0x01010000
#define CFG_MIN_PCI_MEMADDR2 0x01010000
-#define CFG_PCI_PCI_IOADDR 0x01000000
+#define CFG_PCI_PCI_IOADDR 0x01000000
#else
-#define CFG_PCI_DRAM_OFFSET 0x00000000
+#define CFG_PCI_DRAM_OFFSET 0x00000000
#define CFG_60X_PCI_MEM_OFFSET 0x00000000
#define CFG_60X_PCI_IO_OFFSET 0xFE000000
#define CFG_MIN_PCI_MEMADDR1 0xF9000000
#define CFG_MIN_PCI_MEMADDR2 0xFA000000
-#define CFG_PCI_PCI_IOADDR 0x00800000
+#define CFG_PCI_PCI_IOADDR 0x00800000
#endif
-#define CFG_MAX_PCI_DEVICES 32
+#define CFG_MAX_PCI_DEVICES 32
#define CFG_MAX_PCI_FUNCTIONS 8
/*
#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */
-#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
-#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
-#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CFG_ATA_REG_OFFSET 0 /* reg offset */
-#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
+#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */
+#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offset */
+#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
+#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
/*
* ATAPI support (experimental)
* SCSI support (experimental) only SYM53C8xx supported
*/
#define CONFIG_SCSI_SYM53C8XX
-#define CONFIG_SCSI_DEV_ID 0x000F /* 53c875 */
-#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */
-#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+#define CONFIG_SCSI_DEV_ID 0x000F /* 53c875 */
+#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
+#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */
+#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
#define CFG_SCSI_SPIN_UP_TIME 2
#define CFG_SCSI_SCAN_BUS_REVERSE 0
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
-#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
-#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal ide controller */
-#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
-#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
-#define CFG_NS87308_BADDR_10 1
+#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
+#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal ide controller */
+#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
+#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
+#define CFG_NS87308_BADDR_10 1
-#define CFG_NS_PC87308UL 1 /* Nat Semi super-io controller on ISA bus */
+#define CFG_NS_PC87308UL 1 /* Nat Semi super-io controller on ISA bus */
#define CONFIG_RTC_MK48T59
*/
/* do we need the MMU? probably not, but if we do, we must use the BATs */
-#undef CFG_MMU
+#undef CFG_MMU
#ifdef CFG_MMU
/* SDRAM */
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* FLASH organization
* look in include/mpc74xx.h for the defines used here
*/
/*#define CFG_L2*/
-#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)
/*
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */