arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add S3FWRN5 NFC

Some variants of Samsung Galaxy Core Prime LTE / Grand Prime LTE have a
Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver
in the Linux NFC subsystem.

The clock setup for the NFC chip is a bit special (although this
seems to be a common approach used for Qualcomm devices with NFC):

The NFC chip has an output GPIO that is asserted whenever the clock
is needed to function properly. On the A3/A5 this is wired up to
PM8916 GPIO2, which is then configured with a special function
(NFC_CLK_REQ or BB_CLK2_REQ).

Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct
PM8916 to automatically enable the clock whenever the NFC chip
requests it. The advantage is that the clock is only enabled when
needed and we don't need to manage it ourselves from the NFC driver.

Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Link: https://lore.kernel.org/r/20240601115321.25314-3-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi
index 4cc83b64e256147db816a5fd09beaae8015ab61d..b5b7beab220967cf56ad5f4c4887b4e8fc22576a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi
@@ -79,6 +79,35 @@
                max-microvolt = <3300000>;
        };
 
+       i2c_nfc: i2c-nfc {
+               compatible = "i2c-gpio";
+               sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+               pinctrl-0 = <&nfc_i2c_default>;
+               pinctrl-names = "default";
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               s3fwrn5_nfc: nfc@27 {
+                       compatible = "samsung,s3fwrn5-i2c";
+                       reg = <0x27>;
+
+                       interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>;
+
+                       en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+                       wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+
+                       clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+
+                       pinctrl-0 = <&nfc_default>, <&nfc_clk_req>;
+                       pinctrl-names = "default";
+
+                       status = "disabled";
+               };
+       };
+
        reg_motor_vdd: regulator-motor-vdd {
                compatible = "regulator-fixed";
                regulator-name = "motor_vdd";

diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts
index 7ac86fd3c703d1e247b7e20e197e35d275a5aa78..589dd006a746301c3674cf67a8979a75d88a79f7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts
@@ -46,6 +46,10 @@
        };
 };
 
+&i2c_nfc {
+       /* nfc@27 is on &blsp_i2c6 */
+};
+
 &mpss_mem {
        /* Firmware for gprimeltecan needs more space */
        reg = <0x0 0x86800000 0x0 0x5400000>;

diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi
index 13a848d97b9d4d20b7fc64a88b7c553b99ab50b5..e7f265e3c2ab87628d56571a38f3861f8d7d26ef 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi
@@ -33,6 +33,10 @@
        status = "disabled";
 };
 
+&s3fwrn5_nfc {
+       status = "okay";
+};
+
 &st_accel {
        compatible = "st,lis2hh12";
        mount-matrix = "1",  "0", "0",