clk: rockchip: fix wrong mmc sample phase shift for rk3328

mmc sample shift is 0 for RK3328 referring to the TRM.
So fix them.

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 252366a5231f766dd6a9df28fb7a755b7a6021f7..2c54266077907a4cee349fbe9f5a80180477dad5 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -813,22 +813,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
        MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
            RK3328_SDMMC_CON0, 1),
        MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
-           RK3328_SDMMC_CON1, 1),
+           RK3328_SDMMC_CON1, 0),
 
        MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
            RK3328_SDIO_CON0, 1),
        MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
-           RK3328_SDIO_CON1, 1),
+           RK3328_SDIO_CON1, 0),
 
        MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
            RK3328_EMMC_CON0, 1),
        MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
-           RK3328_EMMC_CON1, 1),
+           RK3328_EMMC_CON1, 0),
 
        MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
            RK3328_SDMMC_EXT_CON0, 1),
        MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
-           RK3328_SDMMC_EXT_CON1, 1),
+           RK3328_SDMMC_EXT_CON1, 0),
 };
 
 static const char *const rk3328_critical_clocks[] __initconst = {