clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
        clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
                                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
+       clk[IMX5_CLK_ARM]               = imx_clk_cpu("arm", "cpu_podf",
+                                               clk[IMX5_CLK_CPU_PODF],
+                                               clk[IMX5_CLK_CPU_PODF_SEL],
+                                               clk[IMX5_CLK_PLL1_SW],
+                                               clk[IMX5_CLK_STEP_SEL]);
 
        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
 
 #define IMX5_CLK_SATA_REF              188
 #define IMX5_CLK_STEP_SEL              189
 #define IMX5_CLK_CPU_PODF_SEL          190
-#define IMX5_CLK_END                   191
+#define IMX5_CLK_ARM                   191
+#define IMX5_CLK_END                   192
 
 #endif /* __DT_BINDINGS_CLOCK_IMX5_H */