]> www.infradead.org Git - users/willy/xarray.git/commitdiff
drm/amd/display: Add a config flag for limited_pll_vco
authorJingwen Zhu <Jingwen.Zhu@amd.com>
Mon, 14 Jul 2025 08:18:19 +0000 (16:18 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 28 Jul 2025 20:40:08 +0000 (16:40 -0400)
[Why/How]
Added a new config flag to pass to the DMUB during boot.
This workaround will solves black screen issue on reboot.

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Signed-off-by: Jingwen Zhu <Jingwen.Zhu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

index 0bafb6710761841d99c3d176366a33e4fca8a29e..87b761ac3135da4ce8255db67fc57e13c32b4d0e 100644 (file)
@@ -316,6 +316,7 @@ struct dmub_srv_hw_params {
        bool disable_sldo_opt;
        bool enable_non_transparent_setconfig;
        bool lower_hbr3_phy_ssc;
+       bool override_hbr3_pll_vco;
 };
 
 /**
index a89bf08ffd3799dcdd801357709c6e37a1d1c3d1..e2e5f71c03f2b24a21cfa2620c1b6c17a81f552c 100644 (file)
@@ -843,7 +843,8 @@ union dmub_fw_boot_options {
                uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
                uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
                uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */
-               uint32_t reserved : 6; /**< reserved */
+               uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */
+               uint32_t reserved : 5; /**< reserved */
        } bits; /**< boot bits */
        uint32_t all; /**< 32-bit access to bits */
 };
index 3f38db752b84462c8319b90e581aa6b6be8f5606..4777c7203b2c2deb913197efa914e77918da4aa4 100644 (file)
@@ -377,6 +377,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
        boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;
        boot_options.bits.power_optimization = params->power_optimization;
        boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
+       boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco;
 
        boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;