return;
        }
 
-       if (!ourport->dma || !ourport->dma->tx_chan || count < port->fifosize)
+       if (!ourport->dma || !ourport->dma->tx_chan ||
+           count < ourport->min_dma_size)
                s3c24xx_serial_start_tx_pio(ourport);
        else
                s3c24xx_serial_start_tx_dma(ourport, count);
 
        count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 
-       if (ourport->dma && ourport->dma->tx_chan && count >= port->fifosize) {
+       if (ourport->dma && ourport->dma->tx_chan &&
+           count >= ourport->min_dma_size) {
                s3c24xx_serial_start_tx_dma(ourport, count);
                goto out;
        }
        else if (ourport->info->fifosize)
                ourport->port.fifosize = ourport->info->fifosize;
 
+       /*
+        * DMA transfers must be aligned at least to cache line size,
+        * so find minimal transfer size suitable for DMA mode
+        */
+       ourport->min_dma_size = max_t(int, ourport->port.fifosize,
+                                   dma_get_cache_alignment());
+
        probe_index++;
 
        dbg("%s: initialising port %p...\n", __func__, ourport);