RSND_GEN_S_REG(SSI_MODE1,       0x804),
                RSND_GEN_S_REG(SSI_MODE2,       0x808),
                RSND_GEN_S_REG(SSI_CONTROL,     0x810),
+               RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
+               RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844),
+               RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
+               RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c),
+               RSND_GEN_S_REG(SSI_SYS_STATUS4, 0x880),
+               RSND_GEN_S_REG(SSI_SYS_STATUS5, 0x884),
+               RSND_GEN_S_REG(SSI_SYS_STATUS6, 0x888),
+               RSND_GEN_S_REG(SSI_SYS_STATUS7, 0x88c),
 
                /* FIXME: it needs SSI_MODE2/3 in the future */
                RSND_GEN_M_REG(SSI_BUSIF_MODE,  0x0,    0x80),
 
        RSND_REG_SSI_BUSIF_ADINR,
        RSND_REG_SSI_BUSIF_DALIGN,
        RSND_REG_SSI_INT_ENABLE,
+       RSND_REG_SSI_SYS_STATUS0,
+       RSND_REG_SSI_SYS_STATUS1,
+       RSND_REG_SSI_SYS_STATUS2,
+       RSND_REG_SSI_SYS_STATUS3,
+       RSND_REG_SSI_SYS_STATUS4,
+       RSND_REG_SSI_SYS_STATUS5,
+       RSND_REG_SSI_SYS_STATUS6,
+       RSND_REG_SSI_SYS_STATUS7,
 
        /* SSI */
        RSND_REG_SSICR,
 
        u32 mask1, val1;
        u32 mask2, val2;
 
+       /* clear status */
+       switch (id) {
+       case 0:
+       case 1:
+       case 2:
+       case 3:
+       case 4:
+               rsnd_mod_write(mod, SSI_SYS_STATUS0, 0xf << (id * 4));
+               rsnd_mod_write(mod, SSI_SYS_STATUS2, 0xf << (id * 4));
+               rsnd_mod_write(mod, SSI_SYS_STATUS4, 0xf << (id * 4));
+               rsnd_mod_write(mod, SSI_SYS_STATUS6, 0xf << (id * 4));
+               break;
+       case 9:
+               rsnd_mod_write(mod, SSI_SYS_STATUS1, 0xf << 4);
+               rsnd_mod_write(mod, SSI_SYS_STATUS3, 0xf << 4);
+               rsnd_mod_write(mod, SSI_SYS_STATUS5, 0xf << 4);
+               rsnd_mod_write(mod, SSI_SYS_STATUS7, 0xf << 4);
+               break;
+       }
+
        /*
         * SSI_MODE0
         */