pwm: dwc: make timer clock configurable

Add a configurable clock base rate for the pwm as when being built
for non-PCI the block may be sourced from an internal clock.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230907161242.67190-3-ben.dooks@codethink.co.uk
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c
index 34934b71a75da375a3c4f35a0285812a9a87d100..8e716470390e1fb241c882222c46c0c32a945904 100644 (file)
--- a/drivers/pwm/pwm-dwc-core.c
+++ b/drivers/pwm/pwm-dwc-core.c
@@ -49,13 +49,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
         * periods and check are the result within HW limits between 1 and
         * 2^32 periods.
         */
-       tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS);
+       tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns);
        if (tmp < 1 || tmp > (1ULL << 32))
                return -ERANGE;
        low = tmp - 1;
 
        tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
-                                   DWC_CLK_PERIOD_NS);
+                                   dwc->clk_ns);
        if (tmp < 1 || tmp > (1ULL << 32))
                return -ERANGE;
        high = tmp - 1;
@@ -130,12 +130,12 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
        duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
        duty += 1;
-       duty *= DWC_CLK_PERIOD_NS;
+       duty *= dwc->clk_ns;
        state->duty_cycle = duty;
 
        period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
        period += 1;
-       period *= DWC_CLK_PERIOD_NS;
+       period *= dwc->clk_ns;
        period += duty;
        state->period = period;
 
@@ -159,6 +159,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev)
        if (!dwc)
                return NULL;
 
+       dwc->clk_ns = 10;
        dwc->chip.dev = dev;
        dwc->chip.ops = &dwc_pwm_ops;
        dwc->chip.npwm = DWC_TIMERS_TOTAL;

diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h
index 56deab4e28ecee7496bc7cafd54d7fc3b6027e18..64795247c54ceccc02dc59a73d5fa810884a3b74 100644 (file)
--- a/drivers/pwm/pwm-dwc.h
+++ b/drivers/pwm/pwm-dwc.h
@@ -24,7 +24,6 @@ MODULE_IMPORT_NS(dwc_pwm);
 #define DWC_TIMERS_COMP_VERSION        0xac
 
 #define DWC_TIMERS_TOTAL       8
-#define DWC_CLK_PERIOD_NS      10
 
 /* Timer Control Register */
 #define DWC_TIM_CTRL_EN                BIT(0)
@@ -43,6 +42,7 @@ struct dwc_pwm_ctx {
 struct dwc_pwm {
        struct pwm_chip chip;
        void __iomem *base;
+       unsigned int clk_ns;
        struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
 };
 #define to_dwc_pwm(p)  (container_of((p), struct dwc_pwm, chip))