]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/amdgpu: add option params to enforce process isolation between graphics and compute
authorChong Li <chongli2@amd.com>
Wed, 7 Jun 2023 07:56:12 +0000 (15:56 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 16:49:48 +0000 (12:49 -0400)
enforce process isolation between graphics and compute via using the same reserved vmid.

v2: remove params "struct amdgpu_vm *vm" from
    amdgpu_vmid_alloc_reserved and amdgpu_vmid_free_reserved.

Signed-off-by: Chong Li <chongli2@amd.com>
Reviewed-by: Christian Koenig <Christian.Koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 74104d46a7bea86183d1621b946614843ca69acd..a84bd4a0c42155b46ebbd0278e2588c6d0c4a08f 100644 (file)
@@ -214,6 +214,7 @@ extern int amdgpu_force_asic_type;
 extern int amdgpu_smartshift_bias;
 extern int amdgpu_use_xgmi_p2p;
 extern int amdgpu_mtype_local;
+extern bool enforce_isolation;
 #ifdef CONFIG_HSA_AMD
 extern int sched_policy;
 extern bool debug_evictions;
index 8e58d187b1735b7f39075807fdf4e96b0080b83d..999d008b6b484dbb208a9fe25dd99beacc27d60f 100644 (file)
@@ -153,7 +153,7 @@ uint amdgpu_pg_mask = 0xffffffff;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu;
 char *amdgpu_virtual_display;
-
+bool enforce_isolation;
 /*
  * OverDrive(bit 14) disabled by default
  * GFX DCS(bit 19) disabled by default
@@ -973,6 +973,14 @@ MODULE_PARM_DESC(
                                                4 = AMDGPU_CPX_PARTITION_MODE)");
 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
 
+
+/**
+ * DOC: enforce_isolation (bool)
+ * enforce process isolation between graphics and compute via using the same reserved vmid.
+ */
+module_param(enforce_isolation, bool, 0444);
+MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on");
+
 /* These devices are not supported by amdgpu.
  * They are supported by the mach64, r128, radeon drivers
  */
index c991ca0b7a1c889d6ba705badb54c30126b15e5e..ff1ea99292fbf0185274b08c5b1b2c33689e0a44 100644 (file)
@@ -409,7 +409,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
        if (r || !idle)
                goto error;
 
-       if (vm->reserved_vmid[vmhub]) {
+       if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub == AMDGPU_GFXHUB(0)))) {
                r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence);
                if (r || !id)
                        goto error;
@@ -460,14 +460,11 @@ error:
 }
 
 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
-                              struct amdgpu_vm *vm,
                               unsigned vmhub)
 {
        struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 
        mutex_lock(&id_mgr->lock);
-       if (vm->reserved_vmid[vmhub])
-               goto unlock;
 
        ++id_mgr->reserved_use_count;
        if (!id_mgr->reserved) {
@@ -479,27 +476,23 @@ int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
                list_del_init(&id->list);
                id_mgr->reserved = id;
        }
-       vm->reserved_vmid[vmhub] = true;
 
-unlock:
        mutex_unlock(&id_mgr->lock);
        return 0;
 }
 
 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
-                              struct amdgpu_vm *vm,
                               unsigned vmhub)
 {
        struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 
        mutex_lock(&id_mgr->lock);
-       if (vm->reserved_vmid[vmhub] &&
-           !--id_mgr->reserved_use_count) {
+       if (!--id_mgr->reserved_use_count) {
                /* give the reserved ID back to normal round robin */
                list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);
                id_mgr->reserved = NULL;
        }
-       vm->reserved_vmid[vmhub] = false;
+
        mutex_unlock(&id_mgr->lock);
 }
 
@@ -578,6 +571,10 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
                        list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
                }
        }
+       /* alloc a default reserved vmid to enforce isolation */
+       if (enforce_isolation)
+               amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
+
 }
 
 /**
index d1cc09b45da4a1783edfef7d9f182e247f4f3031..fa8c42c83d5d26bc6d90455b5e7b51b627c5b5d7 100644 (file)
@@ -79,11 +79,9 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
                               struct amdgpu_vmid *id);
 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
-                              struct amdgpu_vm *vm,
-                              unsigned vmhub);
+                               unsigned vmhub);
 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
-                              struct amdgpu_vm *vm,
-                              unsigned vmhub);
+                               unsigned vmhub);
 int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
                     struct amdgpu_job *job, struct dma_fence **fence);
 void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
index 76d57bc7ac6207e4fb089e25ff8af0a64f795ce0..dc80c9c8fd140328246ffb9bd8f74926563e3a40 100644 (file)
@@ -2284,8 +2284,14 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
        }
 
        dma_fence_put(vm->last_update);
-       for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
-               amdgpu_vmid_free_reserved(adev, vm, i);
+
+       for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
+               if (vm->reserved_vmid[i]) {
+                       amdgpu_vmid_free_reserved(adev, i);
+                       vm->reserved_vmid[i] = false;
+               }
+       }
+
 }
 
 /**
@@ -2368,7 +2374,6 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
        union drm_amdgpu_vm *args = data;
        struct amdgpu_device *adev = drm_to_adev(dev);
        struct amdgpu_fpriv *fpriv = filp->driver_priv;
-       int r;
 
        /* No valid flags defined yet */
        if (args->in.flags)
@@ -2377,13 +2382,17 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
        switch (args->in.op) {
        case AMDGPU_VM_OP_RESERVE_VMID:
                /* We only have requirement to reserve vmid from gfxhub */
-               r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
-                                              AMDGPU_GFXHUB(0));
-               if (r)
-                       return r;
+               if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
+                       amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
+                       fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
+               }
+
                break;
        case AMDGPU_VM_OP_UNRESERVE_VMID:
-               amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB(0));
+               if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
+                       amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
+                       fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
+               }
                break;
        default:
                return -EINVAL;