drm/amdgpu: add apu sequence in the imu v11

APU required to issue the enable GFX IMU message after IMU reset.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index abe22749cccc84d21dc97d727381ccd4b12dad45..5f20b41bcb93a784ca2d505d3e91532f3c0847dd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6292,7 +6292,11 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 
 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
 {
-       adev->gfx.imu.mode = DEBUG_MODE;
+       if (adev->flags & AMD_IS_APU)
+               adev->gfx.imu.mode = MISSION_MODE;
+       else
+               adev->gfx.imu.mode = DEBUG_MODE;
+
        adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index fd053158abbdd8f229a067e602346e69cdce19b1..76383baa3929ac7a2cd56bd3c1533a7b05c84aa3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -24,6 +24,7 @@
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_imu.h"
+#include "amdgpu_dpm.h"
 
 #include "gc/gc_11_0_0_offset.h"
 #include "gc/gc_11_0_0_sh_mask.h"
@@ -165,10 +166,10 @@ static int imu_v11_0_start(struct amdgpu_device *adev)
        imu_reg_val &= 0xfffffffe;
        WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-       if (adev->gfx.imu.mode == DEBUG_MODE)
-               return imu_v11_0_wait_for_reset_status(adev);
+       if (adev->flags & AMD_IS_APU)
+               amdgpu_dpm_set_gfx_power_up_by_imu(adev);
 
-       return 0;
+       return imu_v11_0_wait_for_reset_status(adev);
 }
 
 static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =