tg3: Fix link flap at 100Mbps with EEE enabled

This patch increases the scope of the EEE interoperability workaround
to include more asic revisions.  The workarond value is tuned to
workaround a link flap issue at 100Mbps.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit be671947b5b3efc6863ff429c1f265aa38e291db)

Signed-off-by: Joe Jin <joe.jin@oracle.com>

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 8e3d31a2a5fcaf05f796609126d11429f3a7a963..79e8f00dc7e22456f12afe8486cea212ebff0f2f 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3130,15 +3130,16 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
                switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
                case ASIC_REV_5717:
                case ASIC_REV_57765:
-                       if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
-                               tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
-                                                MII_TG3_DSP_CH34TP2_HIBW01);
-                       /* Fall through */
                case ASIC_REV_5719:
                        val = MII_TG3_DSP_TAP26_ALNOKO |
                              MII_TG3_DSP_TAP26_RMRXSTO |
                              MII_TG3_DSP_TAP26_OPCSINPT;
                        tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
+                       /* Fall through */
+               case ASIC_REV_5720:
+                       if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
+                               tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
+                                                MII_TG3_DSP_CH34TP2_HIBW01);
                }
 
                val = 0;

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 3186d86b33f44dc348c0a0c67ccef4bd9c1aef75..81cc62d63abfe029ff463bee93421c65f50d874c 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2180,7 +2180,7 @@
 #define  MII_TG3_DSP_TAP26_OPCSINPT    0x0004
 #define MII_TG3_DSP_AADJ1CH0           0x001f
 #define MII_TG3_DSP_CH34TP2            0x4022
-#define MII_TG3_DSP_CH34TP2_HIBW01     0x017b
+#define MII_TG3_DSP_CH34TP2_HIBW01     0x01ff
 #define MII_TG3_DSP_AADJ1CH3           0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT      0x0f01