target/armv7a: Use LOG_TARGET_xxx()

Use LOG_TARGET_xxx() to indicate which target the message belongs to.

Change-Id: Ic40c61a779c1a1ebdc96ebc56b27541fff5e6205
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8966
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 651241b7720a12653332c75b7688075382f0fd54..2bbafd420ff19e74e397c7c3bbec16ab74513749 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -68,9 +68,9 @@ static void armv7a_show_fault_registers(struct target *target)
        if (retval != ERROR_OK)
                goto done;
 
-       LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
+       LOG_TARGET_USER(target, "Data fault registers        DFSR: %8.8" PRIx32
                ", DFAR: %8.8" PRIx32, dfsr, dfar);
-       LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+       LOG_TARGET_USER(target, "Instruction fault registers IFSR: %8.8" PRIx32
                ", IFAR: %8.8" PRIx32, ifsr, ifar);
 
 done:
@@ -134,7 +134,7 @@ int armv7a_read_ttbcr(struct target *target)
        if (retval != ERROR_OK)
                goto done;
 
-       LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+       LOG_TARGET_DEBUG(target, "ttbcr %" PRIx32, ttbcr);
 
        ttbcr_n = ttbcr & 0x7;
        armv7a->armv7a_mmu.ttbcr = ttbcr;
@@ -169,7 +169,7 @@ int armv7a_read_ttbcr(struct target *target)
                armv7a->armv7a_mmu.ttbr_mask[0]  = 7 << (32 - ttbcr_n);
        }
 
-       LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+       LOG_TARGET_DEBUG(target, "ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
                  (ttbcr_n != 0) ? "used" : "not used",
                  armv7a->armv7a_mmu.ttbr_mask[0],
                  armv7a->armv7a_mmu.ttbr_mask[1]);
@@ -248,14 +248,13 @@ static int armv7a_read_mpidr(struct target *target)
 
        /* Is register in Multiprocessing Extensions register format? */
        if (mpidr & MPIDR_MP_EXT) {
-               LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
+               LOG_TARGET_DEBUG(target, "%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
                armv7a->multi_processor_system = (mpidr >> 30) & 1;
                armv7a->multi_threading_processor = (mpidr >> 24) & 1;
                armv7a->level2_id = (mpidr >> 16) & 0xf;
                armv7a->cluster_id = (mpidr >> 8) & 0xf;
                armv7a->cpu_id = mpidr & 0xf;
-               LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
-                       target_name(target),
+               LOG_TARGET_INFO(target, "MPIDR level2 %x, cluster %x, core %x, %s, %s",
                        armv7a->level2_id,
                        armv7a->cluster_id,
                        armv7a->cpu_id,
@@ -263,7 +262,7 @@ static int armv7a_read_mpidr(struct target *target)
                        armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
        } else
-               LOG_DEBUG("MPIDR not in multiprocessor format");
+               LOG_TARGET_DEBUG(target, "MPIDR not in multiprocessor format");
 
 done:
        dpm->finish(dpm);
@@ -338,7 +337,7 @@ int armv7a_identify_cache(struct target *target)
 
        cache->iminline = 4UL << (ctr & 0xf);
        cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
+       LOG_TARGET_DEBUG(target, "ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
                 ctr, cache->iminline, cache->dminline);
 
        /*  retrieve CLIDR
@@ -350,7 +349,7 @@ int armv7a_identify_cache(struct target *target)
                goto done;
 
        cache->loc = (clidr & 0x7000000) >> 24;
-       LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
+       LOG_TARGET_DEBUG(target, "Number of cache levels to PoC %" PRId32, cache->loc);
 
        /*  retrieve selected cache for later restore
         *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
@@ -378,13 +377,13 @@ int armv7a_identify_cache(struct target *target)
                                goto done;
                        cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+                       LOG_TARGET_DEBUG(target, "data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].d_u_size.index,
                                        cache->arch[cl].d_u_size.index_shift,
                                        cache->arch[cl].d_u_size.way,
                                        cache->arch[cl].d_u_size.way_shift);
 
-                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+                       LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].d_u_size.linelen,
                                        cache->arch[cl].d_u_size.cachesize,
                                        cache->arch[cl].d_u_size.associativity);
@@ -398,13 +397,13 @@ int armv7a_identify_cache(struct target *target)
                                goto done;
                        cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+                       LOG_TARGET_DEBUG(target, "instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].i_size.index,
                                        cache->arch[cl].i_size.index_shift,
                                        cache->arch[cl].i_size.way,
                                        cache->arch[cl].i_size.way_shift);
 
-                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+                       LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].i_size.linelen,
                                        cache->arch[cl].i_size.cachesize,
                                        cache->arch[cl].i_size.associativity);
@@ -445,7 +444,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
                                         armv7a->debug_base + CPUDBG_VCR,
                                         &vcr);
        if (ret < 0) {
-               LOG_ERROR("Failed to read VCR register\n");
+               LOG_TARGET_ERROR(target, "Failed to read VCR register");
                return ret;
        }
 
@@ -458,7 +457,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
                                          armv7a->debug_base + CPUDBG_VCR,
                                          vcr);
        if (ret < 0)
-               LOG_ERROR("Failed to write VCR register\n");
+               LOG_TARGET_ERROR(target, "Failed to write VCR register");
 
        return ret;
 }
@@ -489,18 +488,18 @@ int armv7a_arch_state(struct target *target)
        struct arm *arm = &armv7a->arm;
 
        if (armv7a->common_magic != ARMV7_COMMON_MAGIC) {
-               LOG_ERROR("BUG: called for a non-ARMv7A target");
+               LOG_TARGET_ERROR(target, "BUG: called for a non-ARMv7A target");
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        arm_arch_state(target);
 
        if (armv7a->is_armv7r) {
-               LOG_USER("D-Cache: %s, I-Cache: %s",
+               LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s",
                        state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
                        state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
        } else {
-               LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+               LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s",
                        state[armv7a->armv7a_mmu.mmu_enabled],
                        state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
                        state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);