drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86e8f5649c822ff6fa0502ad88964bfcb269c6c5.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e59de8500d83a2f0895c66769dc360c92492f329..b93953a00deb377e94f4198b4161c2b36bb58eb9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1790,7 +1790,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
                        ALPM_CTL_ALPM_AUX_LESS_ENABLE |
                        ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
 
-               intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
+               intel_de_write(dev_priv,
+                              PORT_ALPM_CTL(dev_priv, cpu_transcoder),
                               PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
                               PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
                               PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
@@ -2116,7 +2117,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
                             ALPM_CTL_ALPM_ENABLE |
                             ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
 
-               intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
+               intel_de_rmw(dev_priv,
+                            PORT_ALPM_CTL(dev_priv, cpu_transcoder),
                             PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
        }
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index bdfe3c596690e2c3425a045ec81737fa4f742b06..eea6abe0ecfa185a8ba80ca906d60909224375b1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -335,7 +335,7 @@
 #define  ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
 
 #define _PORT_ALPM_CTL_A                       0x16fa2c
-#define PORT_ALPM_CTL(tran)                    _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
+#define PORT_ALPM_CTL(dev_priv, tran)                  _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
 #define  PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE    REG_BIT(31)
 #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK        REG_GENMASK(23, 20)
 #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val)        REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)