drm/xe/xe2: Make subsequent L2 flush sequential

Issuing the flush on top of an ongoing flush is not desirable.
Lets use lock to make it sequential.

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240710052750.3031586-1-tejas.upadhyay@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
(cherry picked from commit 71733b8d7f50b61403f940c6c9745fb3a9b98dcb)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 6ce44ca2524de0c261a271b56551784495973cde..c89deffffb6d06019ee17c293c0724546dc66a03 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -865,10 +865,12 @@ void xe_device_l2_flush(struct xe_device *xe)
        if (err)
                return;
 
+       spin_lock(&gt->global_invl_lock);
        xe_mmio_write32(gt, XE2_GLOBAL_INVAL, 0x1);
 
        if (xe_mmio_wait32(gt, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
                xe_gt_err_once(gt, "Global invalidation timeout\n");
+       spin_unlock(&gt->global_invl_lock);
 
        xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
 }

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 816ecc9e294ce99cee633bc226ec32c7dedc28d4..b9bcbbe27705ffdbf1bb9cba276c478857ded24c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -388,6 +388,7 @@ int xe_gt_init_early(struct xe_gt *gt)
 
        xe_force_wake_init_gt(gt, gt_to_fw(gt));
        xe_pcode_init(gt);
+       spin_lock_init(&gt->global_invl_lock);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 6b5e0b45efb0c929218f988146983630c252fbc9..38a0d0e178c8f77a322c3f2aec9b3232e886afd3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -362,6 +362,12 @@ struct xe_gt {
         */
        spinlock_t mcr_lock;
 
+       /**
+        * @global_invl_lock: protects the register for the duration
+        *    of a global invalidation of l2 cache
+        */
+       spinlock_t global_invl_lock;
+
        /** @wa_active: keep track of active workarounds */
        struct {
                /** @wa_active.gt: bitmap with active GT workarounds */