drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA

Disable the workaround inserting an SF symbol between the last DSC EOC
symbol and the subsequent BS symbol. The WA is enabled by default -
based on the register's reset value - and Bspec requires disabling it
explicitly. Bspec doesn't provide an actual WA ID for this.

Bspec: 50054, 65448, 68849

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-6-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cdb7d187830c7b5fa0c75bf51ef3801f3ae2ccb5..1bf13975867e8e68f85e3566ae69d14c6d82b090 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -436,6 +436,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
                intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
                             0, PIPE_ARB_USE_PROG_SLOTS);
 
+       if (DISPLAY_VER(dev_priv) >= 14) {
+               u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
+               u32 set = 0;
+
+               intel_de_rmw(dev_priv,
+                            hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
+                            clear, set);
+       }
+
        val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
        if (val & TRANSCONF_ENABLE) {
                /* we keep both pipes enabled on 830 */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58454e3518f007400fb38c19a7166c2c96050cd0..52111f79ff733b119b5242f8566652d513cc9b44 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4629,6 +4629,7 @@
 #define   DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
 #define   PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
 #define   PSR2_VSC_ENABLE_PROG_HEADER  REG_BIT(12)
+#define   DP_DSC_INSERT_SF_AT_EOL_WA   REG_BIT(4)
 
 #define DISP_ARB_CTL   _MMIO(0x45000)
 #define   DISP_FBC_MEMORY_WAKE         REG_BIT(31)