radeon: use max_bus_speed to activate gen2 speeds

radeon currently uses a drm function to get the speed capabilities for
the bus, drm_pcie_get_speed_cap_mask. However, this is a non-standard
method of performing this detection and this patch changes it to use
the max_bus_speed attribute.

From: Lucas Kannebley Tavares <lucaskt@linux.vnet.ibm.com>
Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 8f9e2d31b25513e1cee9d8a0d24a354c2035df86..8546e3b333b44c2a07314678f4fd1da5c3382c21 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev)
 
 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
 {
-       u32 link_width_cntl, speed_cntl, mask;
-       int ret;
+       u32 link_width_cntl, speed_cntl;
 
        if (radeon_pcie_gen2 == 0)
                return;
@@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
        if (ASIC_IS_X2(rdev))
                return;
 
-       ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-       if (ret != 0)
-               return;
-
-       if (!(mask & DRM_PCIE_SPEED_50))
+       if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+               (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                return;
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1a08008c978bc413fe6e4ac5161c61053ed62c93..b45e64848677a9606a61fea17d440c1a85ea7f09 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
 {
        u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
        u16 link_cntl2;
-       u32 mask;
-       int ret;
 
        if (radeon_pcie_gen2 == 0)
                return;
@@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
        if (rdev->family <= CHIP_R600)
                return;
 
-       ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-       if (ret != 0)
-               return;
-
-       if (!(mask & DRM_PCIE_SPEED_50))
+       if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+               (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                return;
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 3fc2985445eebac8537a9770782047c32f66dec1..08aef24afe401601070c52800c7d8551f2c5b225 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -2111,8 +2111,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
 {
        u32 link_width_cntl, lanes, speed_cntl, tmp;
        u16 link_cntl2;
-       u32 mask;
-       int ret;
 
        if (radeon_pcie_gen2 == 0)
                return;
@@ -2127,11 +2125,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
        if (ASIC_IS_X2(rdev))
                return;
 
-       ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-       if (ret != 0)
-               return;
-
-       if (!(mask & DRM_PCIE_SPEED_50))
+       if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+               (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                return;
 
        DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");