drm/msm/dpu: remove DPU_DSPP_IGC handling in dspp flush

Inverse gamma correction blocks (IGC) are not used today so lets
remove the usage of DPU_DSPP_IGC in the DSPP flush to make it easier
to remove IGC from the catalog.

We can add this back when IGC is properly supported in DPU with
one of the standard DRM properties.

changes in v3:
	- minor change dspp -> DSPP in commit text

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/534724/
Link: https://lore.kernel.org/r/20230428223646.23595-2-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index cfdefacbc5a241b84807285dfe13bc315a8086ea..07bcacedf4b0206217fe6916a03019e976be590b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -313,9 +313,6 @@ static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks(
                return;
 
        switch (dspp_sub_blk) {
-       case DPU_DSPP_IGC:
-               ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(2);
-               break;
        case DPU_DSPP_PCC:
                ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4);
                break;