* "last user address" is set even if bootp is used without parameters
(and it uses default address).
+======================================================================
+Modifications for 1.1.3:
+======================================================================
+
+* Add MUSENKI board; add some 8245 and 8241 related stuff.
+ Patch by Jim Thompson, 10 Dec 2001
+
+* Better support for SBC8260 Board:
+ - allow compilation with DEBUG defined
+ - support configuration where ethernet is on the SCC
+ - add support for setting the last octect of the ethernet address
+ from the user definable dip switches (DS0-DS7)
+ Note: The SBC8260 PPCBoot can be used on the SBC8255. All that
+ needs to be done is to set the correct frequency.
+ Patch by Brad Kemp, 14 Dec 2001
+
+* Configure PCMCIA support for FADS860 board
+ Patch by Jeremy Rosen, 07 Dec 2001
+
+* Fix bug in CU824 flash driver
+
======================================================================
Modifications for 1.1.2:
======================================================================
E: etheisen@mindspring.com
D: MBX8xx and many other patches
+N: Jim Thompson
+E: jim@musenki.com
+D: Support for MUSENKI board
+
N: David Updegraff
E: dave@cray.com
D: Port to Cray L1 board; DHCP vendor extensions
LIST_824x=" \
CU824 \
MOUSSE \
+ MUSENKI \
Sandpoint8240 \
"
echo "CPU = mpc824x" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+MUSENKI_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd ./include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = musenki" >>config.mk ; \
+ echo "CPU = mpc824x" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
Sandpoint8240_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
echo "CPU = mpc824x" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+
#########################################################################
## MPC8260 Systems
#########################################################################
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-static int write_data (flash_info_t *info, ulong dest, uchar *data);
-static void write_via_fpu(volatile ulong *addr, uchar *data);
+static int write_data (flash_info_t *info, ulong dest, ulong *data);
+static void write_via_fpu(vu_long *addr, ulong *data);
static __inline__ unsigned long get_msr(void);
static __inline__ void set_msr(unsigned long msr);
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
- int i, j;
- unsigned long size = 0;
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ addr[0] = 0x00900090;
+
+ DEBUGF ("Flash bank # %d:\n"
+ "\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+ "\tDevice ID @ 0x%08lX: 0x%08lX\n",
+ i,
+ (ulong)(&addr[0]), addr[0],
+ (ulong)(&addr[2]), addr[2]);
+
+ if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+ (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B))
{
- *(volatile u_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE) =
- 0x00900090;
- if (*(volatile u_long *)(CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE) ==
- *(volatile u_long *)(CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE + 4) &&
- *(volatile u_long *)(CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE) ==
- 0x00890089 &&
- *(volatile u_long *)(CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE + 8) ==
- *(volatile u_long *)(CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE + 12) &&
- *(volatile u_long *)(CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE + 8) ==
- 0x88f488f4)
- {
- flash_info[i].flash_id = 0x008988F4;
- }
- else
- {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- goto Done;
- }
- *(volatile u_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE) =
- 0xffffffff;
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
- for (j = 0; j < flash_info[i].sector_count; j++)
- {
- if (j <= 7)
- {
- flash_info[i].start[j] = CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- j * PARAM_SECT_SIZE;
- }
- else
- {
- flash_info[i].start[j] = CFG_FLASH_BASE +
- i * FLASH_BANK_SIZE +
- (j - 7)*MAIN_SECT_SIZE;
- }
+ flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
+ (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
+ } else {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ addr[0] = 0xFFFFFFFF;
+ goto Done;
+ }
+
+ DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+ addr[0] = 0xFFFFFFFF;
+
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ if (j <= 7) {
+ flash_info[i].start[j] = CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE +
+ j * PARAM_SECT_SIZE;
+ } else {
+ flash_info[i].start[j] = CFG_FLASH_BASE +
+ i * FLASH_BANK_SIZE +
+ (j - 7)*MAIN_SECT_SIZE;
}
- size += flash_info[i].size;
}
+ size += flash_info[i].size;
+ }
- /* Protect monitor and environment sectors
- */
+ /* Protect monitor and environment sectors
+ */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
- &flash_info[1]);
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[1]);
#else
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
- &flash_info[0]);
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
#endif
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- &flash_info[1]);
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[1]);
#else
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- &flash_info[0]);
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
#endif
#endif
- Done:
- return size;
+Done:
+ return size;
}
/*-----------------------------------------------------------------------
*/
-void flash_print_info (flash_info_t *info)
+void flash_print_info (flash_info_t * info)
{
int i;
- switch (info->flash_id & FLASH_VENDMASK)
- {
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf("Intel: ");
+ switch ((i = info->flash_id & FLASH_VENDMASK)) {
+ case (FLASH_MAN_INTEL & FLASH_VENDMASK):
+ printf ("Intel: ");
+ break;
+ default:
+ printf ("Unknown Vendor 0x%04x ", i);
break;
- default:
- printf("Unknown Vendor ");
- break;
}
- switch (info->flash_id & FLASH_TYPEMASK)
- {
- case 0x88F4:
- printf("28F160F3B (16Mbit)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- goto Done;
- break;
+ switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+ case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
+ printf ("28F160F3B (16Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type 0x%04x\n", i);
+ goto Done;
+ break;
}
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++)
- {
- if ((i % 5) == 0)
- {
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
+ info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
- Done:
- return;
+Done:
+ return;
}
/*-----------------------------------------------------------------------
int flag, prot, sect;
ulong start, now, last;
+ DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+ info - &flash_info[0], s_first, s_last);
+
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
}
if ((info->flash_id & FLASH_VENDMASK) !=
- (INTEL_MANUFACT & FLASH_VENDMASK)) {
+ (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
printf ("Can erase only Intel flash types - aborted\n");
return 1;
}
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *)(info->start[sect]);
- unsigned long status;
+
+ DEBUGF ("Erase sect %d @ 0x%08lX\n",
+ sect, (ulong)addr);
/* Disable interrupts which might cause a timeout
* here.
*/
flag = disable_interrupts();
- *addr = 0x00500050; /* clear status register */
- *addr = 0x00200020; /* erase setup */
- *addr = 0x00D000D0; /* erase confirm */
+ addr[0] = 0x00500050; /* clear status register */
+ addr[0] = 0x00200020; /* erase setup */
+ addr[0] = 0x00D000D0; /* erase confirm */
/* re-enable interrupts if necessary */
if (flag)
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
- while (((status = *addr) & 0x00800080) != 0x00800080) {
+ while (((addr[0] & 0x00800080) != 0x00800080) ||
+ ((addr[1] & 0x00800080) != 0x00800080) ) {
if ((now=get_timer(start)) >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
- *addr = 0x00B000B0; /* suspend erase */
- *addr = 0x00FF00FF; /* to read mode */
+ addr[0] = 0x00B000B0; /* suspend erase */
+ addr[0] = 0x00FF00FF; /* to read mode */
return 1;
}
}
}
- *addr = 0x00FF00FF; /* reset to read mode */
+ addr[0] = 0x00FF00FF;
}
}
printf (" done\n");
{
ulong wp, cp, msr;
int l, rc, i;
- unsigned char data[8];
- u_long *datah = (u_long *)&data[0];
- u_long *datal = (u_long *)&data[4];
+ ulong data[2];
+ ulong *datah = &data[0];
+ ulong *datal = &data[1];
+
+ DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+ addr, (ulong)src, cnt);
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
((*datal & 0xFF000000) >> 24);
}
- *datal = (*datal << 8) | (*(u_char *)cp);
+ *datal = (*datal << 8) | (*(uchar *)cp);
}
for (; i < FLASH_WIDTH && cnt > 0; ++i) {
char tmp;
((*datal & 0xFF000000) >> 24);
}
- *datal = (*datah << 8) | (*(u_char *)cp);
+ *datal = (*datah << 8) | (*(uchar *)cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
* handle FLASH_WIDTH aligned part
*/
while (cnt >= FLASH_WIDTH) {
- *datah = *(u_long *)src;
- *datal = *(u_long *)(src + 4);
+ *datah = *(ulong *)src;
+ *datal = *(ulong *)(src + 4);
if ((rc = write_data(info, wp, data)) != 0) {
set_msr(msr);
return (rc);
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
}
- *datal = (*datal << 8) | (*(u_char *)cp);
+ *datal = (*datal << 8) | (*(uchar *)cp);
}
rc = write_data(info, wp, data);
set_msr(msr);
+
return (rc);
}
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_data (flash_info_t *info, ulong dest, uchar *data)
+static int write_data (flash_info_t *info, ulong dest, ulong *data)
{
vu_long *addr = (vu_long *)dest;
- ulong status;
ulong start;
- ulong *hdata = (ulong *)&data[0];
- ulong *ldata = (ulong *)&data[4];
int flag;
/* Check if Flash is (sufficiently) erased */
- if ((*addr & *hdata) != *hdata ||
- (*(addr + 1) & *ldata) != *ldata) {
+ if (((addr[0] & data[0]) != data[0]) ||
+ ((addr[1] & data[1]) != data[1]) ) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- *addr = 0x00400040; /* write setup */
+ addr[0] = 0x00400040; /* write setup */
write_via_fpu(addr, data);
/* re-enable interrupts if necessary */
start = get_timer (0);
- while ((((status = *addr) & 0x00800080) != 0x00800080) ||
- ((*(addr + 1)) & 0x00800080) != 0x00800080) {
+ while (((addr[0] & 0x00800080) != 0x00800080) ||
+ ((addr[1] & 0x00800080) != 0x00800080) ) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- *addr = 0x00FF00FF; /* restore read mode */
+ addr[0] = 0x00FF00FF; /* restore read mode */
return (1);
}
}
- *addr = 0x00FF00FF; /* restore read mode */
+ addr[0] = 0x00FF00FF; /* restore read mode */
return (0);
}
/*-----------------------------------------------------------------------
*/
-static void write_via_fpu(volatile ulong *addr, uchar *data)
+static void write_via_fpu(vu_long *addr, ulong *data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
{
unsigned long msr;
- asm volatile("mfmsr %0" : "=r" (msr) :);
+ __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
{
- asm volatile("mtmsr %0" : : "r" (msr));
+ __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
}
-
-
#include <ppcboot.h>
#include <mpc8xx.h>
-typedef volatile unsigned char vu_char;
-
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
#include <ppcboot.h>
#include <mpc8xx.h>
-typedef volatile unsigned char vu_char;
-
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
#include <ppcboot.h>
#include <mpc8xx.h>
-typedef volatile unsigned char vu_char;
-
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
#include <ppcboot.h>
-typedef volatile unsigned char vu_char;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o ns16550.o serial.o speed.o dc2114x.o
+SOBJS = early_init.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+ppcboot for a Musenki M-3/M-1 board
+---------------------------
+
+Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each.
+
+In board's notation, bank 0 is the one at the address of 0xFF800000
+and bank 1 is the one at the address of 0xFF000000.
+
+On power-up the processor jumps to the address of 0xFFF00100, the last
+megabyte of the bank 0 of flash.
+
+Thus, PPCBoot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is located in flash separately from
+PPCBoot, at the address of 0xFF800000.
+
+There is a Davicom 9102A on-board, but I don't have it working yet.
+
+PPCBoot test results
+--------------------
+
+x.x Operation on all available serial consoles
+
+x.x.x CONFIG_CONS_INDEX 1
+
+
+PPCBoot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=> help
+autoscr - run script from memory
+base - print or set address offset
+bdinfo - print Board Info structure
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootd - boot default, i.e., run 'bootcmd'
+cmp - memory compare
+coninfo - print console devices and informations
+cp - memory copy
+crc32 - checksum calculation
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loop - infinite loop on address range
+md - memory display
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nm - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+tftpboot- boot image via network using TFTP protocol
+ and env variables ipaddr and serverip
+version - print monitor version
+? - alias for 'help'
+
+
+
+x.x.x CONFIG_CONS_INDEX 2
+
+**** NOT TESTED ****
+
+x.x Flash Driver Operation
+
+
+Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+*** Warning - bad CRC, using default environment
+
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=>
+=> md ff800000
+ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot
+ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd
+ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate=
+ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m
+ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria
+ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial.
+ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip
+ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4
+ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1
+ff800090: 36382e30 2e380000 00000000 00000000 68.0.8..........
+ff8000a0: 00000000 00000000 00000000 00000000 ................
+ff8000b0: 00000000 00000000 00000000 00000000 ................
+ff8000c0: 00000000 00000000 00000000 00000000 ................
+ff8000d0: 00000000 00000000 00000000 00000000 ................
+ff8000e0: 00000000 00000000 00000000 00000000 ................
+ff8000f0: 00000000 00000000 00000000 00000000 ................
+=> protect off ff800000 ff81ffff
+Un-Protected 1 sectors
+=> erase ff800000 ff81ffff
+Erase Flash from 0xff800000 to 0xff81ffff
+ done
+Erased 1 sectors
+=> md ff800000
+ff800000: ffffffff ffffffff ffffffff ffffffff ................
+ff800010: ffffffff ffffffff ffffffff ffffffff ................
+ff800020: ffffffff ffffffff ffffffff ffffffff ................
+ff800030: ffffffff ffffffff ffffffff ffffffff ................
+ff800040: ffffffff ffffffff ffffffff ffffffff ................
+ff800050: ffffffff ffffffff ffffffff ffffffff ................
+ff800060: ffffffff ffffffff ffffffff ffffffff ................
+ff800070: ffffffff ffffffff ffffffff ffffffff ................
+ff800080: ffffffff ffffffff ffffffff ffffffff ................
+ff800090: ffffffff ffffffff ffffffff ffffffff ................
+ff8000a0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000b0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000c0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000d0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000e0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000f0: ffffffff ffffffff ffffffff ffffffff ................
+
+x.x.x Information
+
+
+PPCBoot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+*** Warning - bad CRC, using default environment
+
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=> flinfo
+
+Bank # 1: Intel 28F320JA3 (32Mbit = 128K x 32)
+ Size: 4 MB in 32 Sectors
+ Sector Start Addresses:
+ FF800000 (RO) FF820000 FF840000 FF860000 FF880000
+ FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000
+ FF940000 FF960000 FF980000 FF9A0000 FF9C0000
+ FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000
+ FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000
+ FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000
+ FFBC0000 FFBE0000
+
+Bank # 2: missing or unknown FLASH type
+=>
+
+
+
+x.x.x Flash Programming
+
+
+PPCBoot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=>
+=>
+=>
+=> protect off ff800000 ff81ffff
+Un-Protected 1 sectors
+=> cp 0 ff800000 20
+Copy to Flash... done
+=> md ff800000
+ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5.
+ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6.
+ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3.
+ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3.
+ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3.
+ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3.....
+ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w.
+ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3.
+ff800080: ffffffff ffffffff ffffffff ffffffff ................
+ff800090: ffffffff ffffffff ffffffff ffffffff ................
+ff8000a0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000b0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000c0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000d0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000e0: ffffffff ffffffff ffffffff ffffffff ................
+ff8000f0: ffffffff ffffffff ffffffff ffffffff ................
+
+
+x.x.x Storage of environment variables in flash
+
+
+PPCBoot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=> printenv
+bootcmd=bootm FF820000
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 106/16380 bytes
+=> setenv myvar 1234
+=> saveenv
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=> reset
+
+
+PPCBoot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=> printenv
+bootcmd=bootm FF820000
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+myvar=1234
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 117/16380 bytes
+
+x.x Image Download and run over serial port
+
+
+PPCBoot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM: 32 MB
+FLASH: 4 MB
+In: serial
+Out: serial
+Err: serial
+Hit any key to stop autoboot: 0
+=> loads
+## Ready for S-Record download ...
+
+## First Load Addr = 0x00040000
+## Last Load Addr = 0x00050177
+## Total Size = 0x00010178 = 65912 Bytes
+## Start Addr = 0x00040004
+=> go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+
+
+x.x Image download and run over ethernet interface
+
+untested (not working yet, actually)
+
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CU824 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <net.h>
+
+ /* PCI Registers.
+ */
+#define PCI_VENDOR_ID 0x00
+#define PCI_COMMAND 0x04
+#define PCI_CLASS_REVISION 0x08
+#define PCI_LATENCY_TIMER 0x0d
+#define PCI_BASE_ADDRESS_0 0x10
+#define PCI_CFDA_PSM 0x43
+
+#define PCI_COMMAND_IO 0x1
+#define PCI_COMMAND_MASTER 0x4
+
+#define CFRV_RN 0x000000f0 /* Revision Number */
+#define CBIO_MASK -128
+
+#define WAKEUP 0x00 /* Power Saving Wakeup */
+#define SLEEP 0x80 /* Power Saving Sleep Mode */
+
+
+#define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */
+#define DC2114x_DID 0x1900 /* Unique Device ID # */
+#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
+#define DC21142 (DC2114x_DID | 0x0010)
+#define DC21143 (DC2114x_DID | 0x0030)
+
+#define DAVICOM_VID 0x1282 /* DC2114[23] Manufacturer */
+#define DAVICOM_DID 0x9102 /* Unique Device ID # */
+
+#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID))
+#define is_DAVICOM ((vendor == DAVICOM_VID) && (device == DAVICOM_DID))
+
+
+ /* Ethernet chip registers.
+ */
+#define DE4X5_BMR iobase + 0x000 /* Bus Mode Register */
+#define DE4X5_TPD iobase + 0x008 /* Transmit Poll Demand Reg */
+#define DE4X5_RRBA iobase + 0x018 /* RX Ring Base Address Reg */
+#define DE4X5_TRBA iobase + 0x020 /* TX Ring Base Address Reg */
+#define DE4X5_STS iobase + 0x028 /* Status Register */
+#define DE4X5_OMR iobase + 0x030 /* Operation Mode Register */
+#define DE4X5_SICR iobase + 0x068 /* SIA Connectivity Register */
+#define DE4X5_APROM iobase + 0x048 /* Ethernet Address PROM */
+
+ /* Register bits.
+ */
+#define BMR_SWR 0x00000001 /* Software Reset */
+#define STS_TS 0x00700000 /* Transmit Process State */
+#define STS_RS 0x000e0000 /* Receive Process State */
+#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
+#define OMR_SR 0x00000002 /* Start/Stop Receive */
+#define OMR_PS 0x00040000 /* Port Select */
+#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
+#define OMR_PM 0x00000080 /* Pass All Multicast */
+
+ /* Descriptor bits.
+ */
+#define R_OWN 0x80000000 /* Own Bit */
+#define RD_RER 0x02000000 /* Receive End Of Ring */
+#define RD_LS 0x00000100 /* Last Descriptor */
+#define RD_ES 0x00008000 /* Error Summary */
+#define TD_TER 0x02000000 /* Transmit End Of Ring */
+#define T_OWN 0x80000000 /* Own Bit */
+#define TD_LS 0x40000000 /* Last Segment */
+#define TD_FS 0x20000000 /* First Segment */
+#define TD_ES 0x00008000 /* Error Summary */
+#define TD_SET 0x08000000 /* Setup Packet */
+
+
+#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
+#define SROM_RD 0x00004000 /* Read from Boot ROM */
+#define SROM_SR 0x00000800 /* Select Serial ROM when set */
+
+#define DT_IN 0x00000004 /* Serial Data In */
+#define DT_CLK 0x00000002 /* Serial ROM Clock */
+#define DT_CS 0x00000001 /* Serial ROM Chip Select */
+
+#define POLL_DEMAND 1
+
+#define RESET_DE4X5 {\
+ int i;\
+ i=inl(DE4X5_BMR);\
+ udelay(1000);\
+ outl(i | BMR_SWR, DE4X5_BMR);\
+ udelay(1000);\
+ outl(i, DE4X5_BMR);\
+ udelay(1000);\
+ for (i=0;i<5;i++) {inl(DE4X5_BMR); udelay(10000);}\
+ udelay(1000);\
+}
+
+#define START_DE4X5 {\
+ s32 omr; \
+ omr = inl(DE4X5_OMR);\
+ omr |= OMR_ST | OMR_SR;\
+ outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
+}
+
+#define STOP_DE4X5 {\
+ s32 omr; \
+ omr = inl(DE4X5_OMR);\
+ omr &= ~(OMR_ST|OMR_SR);\
+ outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
+}
+
+#define NUM_RX_DESC PKTBUFSRX
+#define NUM_TX_DESC 1 /* Number of TX descriptors */
+#define RX_BUFF_SZ PKTSIZE_ALIGN
+
+#define TOUT_LOOP 1000000
+
+#define SETUP_FRAME_LEN 192
+#define ETH_ALEN 6
+
+
+struct de4x5_desc {
+ volatile s32 status;
+ u32 des1;
+ u32 buf;
+ u32 next;
+};
+
+
+static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
+static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
+static int rx_new; /* RX descriptor ring pointer */
+static int tx_new; /* TX descriptor ring pointer */
+
+static char rxRingSize;
+static char txRingSize;
+
+static u_long iobase;
+
+static void send_setup_frame(bd_t * bis);
+static void check_hw_addr(bd_t * bis);
+static short srom_rd(u_long address, u_char offset);
+static void srom_latch(u_int command, u_long address);
+static void srom_command(u_int command, u_long address);
+static void srom_address(u_int command, u_long address, u_char offset);
+static short srom_data(u_int command, u_long address);
+static void sendto_srom(u_int command, u_long addr);
+static int getfrom_srom(u_long addr);
+
+static inline int inl(u_long addr)
+{
+ return le32_to_cpu(*(volatile u_long *)(addr + 0xfe000000));
+}
+
+static inline void outl (int command, u_long addr)
+{
+ *(volatile u_long *)(addr + 0xfe000000) = cpu_to_le32(command);
+}
+
+int eth_init(bd_t *bis)
+{
+ int i, status = 0;
+ int vendor, device, l;
+ int cfrv;
+ unsigned char timer;
+
+
+ CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN, l);
+
+ l >>= 8;
+
+ if (l != 0x00020000)
+ {
+ printf("Error: Can not find an ethernet card on the PCI bus %d "
+ "in slot %d\n", CFG_ETH_DEV_FN >> 16,
+ (CFG_ETH_DEV_FN & 0xFFFF) >> 11);
+ goto Done;
+ }
+
+ CONFIG_READ_WORD(0x80000000 | PCI_VENDOR_ID | CFG_ETH_DEV_FN, vendor);
+
+ device = (vendor >> 16) & 0xffff;
+ vendor = vendor & 0xffff;
+ device = device << 8;
+
+ if (!(is_DAVICOM))
+ {
+ printf("Error: The chip is not DAVICOM.\n");
+ goto Done;
+ }
+
+ /* Get the chip configuration revision register.
+ */
+ CONFIG_READ_WORD(0x80000000 | PCI_CLASS_REVISION | CFG_ETH_DEV_FN,
+ cfrv);
+
+ device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
+
+ if (device != 0x9102)
+ {
+ printf("Error: The chip is not a DM92102F.\n");
+ goto Done;
+ }
+
+ /* Check if I/O accesses and Bus Mastering are enabled.
+ */
+ CONFIG_READ_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN, status);
+
+ if (!(status & PCI_COMMAND_IO))
+ {
+ status |= PCI_COMMAND_IO;
+ CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN,
+ status);
+ CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN,
+ status);
+ }
+
+ if (!(status & PCI_COMMAND_IO))
+ {
+ printf("Error: Can not enable I/O access.\n");
+ goto Done;
+ }
+
+ if (!(status & PCI_COMMAND_MASTER))
+ {
+ status |= PCI_COMMAND_MASTER;
+ CONFIG_WRITE_HALFWORD(0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN,
+ status);
+ CONFIG_READ_HALFWORD( 0x80000000 | PCI_COMMAND | CFG_ETH_DEV_FN,
+ status);
+ }
+ if (!(status & PCI_COMMAND_MASTER))
+ {
+ printf("Error: Can not enable Bus Mastering.\n");
+ goto Done;
+ }
+
+ /* Check the latency timer for values >= 0x60.
+ */
+ CONFIG_READ_BYTE(0x80000000 | PCI_LATENCY_TIMER | CFG_ETH_DEV_FN,
+ timer);
+ if (timer < 0x60)
+ {
+ CONFIG_WRITE_BYTE(0x80000000 | PCI_LATENCY_TIMER |
+ CFG_ETH_DEV_FN,
+ 0X60);
+ }
+
+ /* Set I/O base register.
+ */
+ CONFIG_WRITE_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN,
+ CFG_ETH_IOBASE);
+
+ CONFIG_READ_WORD(0x80000000 | PCI_BASE_ADDRESS_0 | CFG_ETH_DEV_FN,
+ iobase);
+
+ if (iobase == 0xffffffff)
+ {
+ printf("Error: Can not set I/O base register.\n");
+ goto Done;
+ }
+
+ iobase &= CBIO_MASK;
+
+ /* Ensure we're not sleeping.
+ */
+ CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, WAKEUP);
+
+ udelay(10 * 1000);
+
+ check_hw_addr(bis);
+
+ RESET_DE4X5;
+
+ if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0)
+ {
+ printf("Error: Can not reset ethernet controller.\n");
+ goto Done;
+ }
+
+ outl(OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+
+ for (i = 0; i < NUM_RX_DESC; i++)
+ {
+ rx_ring[i].status = cpu_to_le32(R_OWN);
+ rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
+ rx_ring[i].buf = cpu_to_le32((u_long)NetRxPackets[i]);
+ rx_ring[i].next = 0;
+ }
+
+ for (i=0; i < NUM_TX_DESC; i++)
+ {
+ tx_ring[i].status = 0;
+ tx_ring[i].des1 = 0;
+ tx_ring[i].buf = 0;
+ tx_ring[i].next = 0;
+ }
+
+ rxRingSize = NUM_RX_DESC;
+ txRingSize = NUM_TX_DESC;
+
+ /* Write the end of list marker to the descriptor lists.
+ */
+ rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
+ tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
+
+ /* Tell the adapter where the TX/RX rings are located.
+ */
+ outl((u_long)&rx_ring, DE4X5_RRBA);
+ outl((u_long)&tx_ring, DE4X5_TRBA);
+
+ START_DE4X5;
+
+ tx_new = 0;
+ rx_new = 0;
+
+ send_setup_frame(bis);
+
+Done:
+
+ return 0;
+}
+
+int eth_send(volatile void *packet, int length)
+{
+ int status = 0;
+ int i;
+
+ if (length <= 0)
+ {
+ printf("eth: bad packet size: %d\n", length);
+ goto out;
+ }
+
+ for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: tx error buffer not ready\n");
+ goto out;
+ }
+ }
+
+ tx_ring[tx_new].buf = cpu_to_le32((u_long)packet);
+ tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
+ tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+ outl(POLL_DEMAND, DE4X5_TPD);
+
+ for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: tx buffer not ready\n");
+ goto out;
+ }
+ }
+
+ if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES)
+ {
+#if 0
+ printf("TX error status = 0x%08X\n",
+ le32_to_cpu(tx_ring[tx_new].status));
+#endif
+ status++;
+ }
+
+ out:
+ return status;
+}
+
+int eth_rx(void)
+{
+ s32 status;
+ int length = 0;
+
+ for ( ; ; )
+ {
+ status = (s32)le32_to_cpu(rx_ring[rx_new].status);
+
+ if (status & R_OWN)
+ {
+ break;
+ }
+
+ if (status & RD_LS)
+ {
+ /* Valid frame status.
+ */
+ if (status & RD_ES)
+ {
+ /* There was an error.
+ */
+ printf("RX error status = 0x%08X\n", status);
+ }
+ else
+ {
+ /* A valid frame received.
+ */
+ length = (le32_to_cpu(rx_ring[rx_new].status) >>
+ 16);
+
+ /* Pass the packet up to the protocol
+ * layers.
+ */
+ NetReceive(NetRxPackets[rx_new], length - 4);
+ }
+
+ /* Change buffer ownership for this frame, back
+ * to the adapter.
+ */
+ rx_ring[rx_new].status = cpu_to_le32(R_OWN);
+ }
+
+ /* Update entry information.
+ */
+ rx_new = (++rx_new) % rxRingSize;
+ }
+
+ return length;
+}
+
+void eth_halt(void)
+{
+ if (iobase != CFG_ETH_IOBASE) {
+ /* Ethernet has not been initialized yet. */
+ return;
+ }
+
+ STOP_DE4X5;
+ outl(0, DE4X5_SICR);
+ CONFIG_WRITE_BYTE(0x80000000 | CFG_ETH_DEV_FN | PCI_CFDA_PSM, SLEEP);
+}
+
+static void check_hw_addr(bd_t *bis)
+{
+ unsigned char hw_addr[ETH_ALEN];
+ u_short tmp, *p = (short *)(&hw_addr[0]);
+ int i, j = 0;
+
+ for (i = 0; i < (ETH_ALEN >> 1); i++)
+ {
+ tmp = srom_rd(DE4X5_APROM, (SROM_HWADD >> 1) + i);
+ *p = le16_to_cpu(tmp);
+ j += *p++;
+ }
+
+ if ((j == 0) || (j == 0x2fffd))
+ {
+ printf("Warning: can't read HW address from SROM.\n");
+ goto Done;
+ }
+
+ for (i = 0; i < ETH_ALEN; i++)
+ {
+ if (hw_addr[i] != bis->bi_enetaddr[i])
+ {
+ printf("Warning: HW addresses don't match:\n");
+ printf("Address in SROM is "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ hw_addr[0], hw_addr[1], hw_addr[2],
+ hw_addr[3], hw_addr[4], hw_addr[5]);
+ printf("Address used by ppcboot is "
+ "%02X:%02X:%02X:%02X:%02X:%02X\n",
+ bis->bi_enetaddr[0], bis->bi_enetaddr[1],
+ bis->bi_enetaddr[2], bis->bi_enetaddr[3],
+ bis->bi_enetaddr[4], bis->bi_enetaddr[5]);
+ goto Done;
+ }
+ }
+
+ Done:
+}
+
+static void send_setup_frame(bd_t *bis)
+{
+ int i;
+ char setup_frame[SETUP_FRAME_LEN];
+ char * pa = &setup_frame[0];
+
+ memset(pa, 0xff, SETUP_FRAME_LEN);
+
+ for (i = 0; i < ETH_ALEN; i++)
+ {
+ *(pa + (i & 1)) = bis->bi_enetaddr[i];
+ if (i & 0x01)
+ {
+ pa += 4;
+ }
+ }
+
+ for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: tx error buffer not ready\n");
+ goto out;
+ }
+ }
+
+ tx_ring[tx_new].buf = cpu_to_le32((u_long)&setup_frame[0]);
+ tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
+ tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+ outl(POLL_DEMAND, DE4X5_TPD);
+
+ for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++)
+ {
+ if (i >= TOUT_LOOP)
+ {
+ printf("eth: tx buffer not ready\n");
+ goto out;
+ }
+ }
+
+#if 0
+ if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF)
+ {
+ printf("TX error status = 0x%08X\n",
+ le32_to_cpu(tx_ring[tx_new].status));
+ }
+#endif
+ out:
+}
+
+ /* SROM Read.
+ */
+static short
+srom_rd(u_long addr, u_char offset)
+{
+ sendto_srom(SROM_RD | SROM_SR, addr);
+
+ srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
+ srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
+ srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
+
+ return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
+}
+
+static void
+srom_latch(u_int command, u_long addr)
+{
+ sendto_srom(command, addr);
+ sendto_srom(command | DT_CLK, addr);
+ sendto_srom(command, addr);
+
+ return;
+}
+
+static void
+srom_command(u_int command, u_long addr)
+{
+ srom_latch(command, addr);
+ srom_latch(command, addr);
+ srom_latch((command & 0x0000ff00) | DT_CS, addr);
+
+ return;
+}
+
+static void
+srom_address(u_int command, u_long addr, u_char offset)
+{
+ int i;
+ signed char a;
+
+ a = (char)(offset << 2);
+ for (i=0; i<6; i++, a <<= 1) {
+ srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
+ }
+ udelay(1);
+
+ i = (getfrom_srom(addr) >> 3) & 0x01;
+
+ return;
+}
+
+static short
+srom_data(u_int command, u_long addr)
+{
+ int i;
+ short word = 0;
+ s32 tmp;
+
+ for (i=0; i<16; i++) {
+ sendto_srom(command | DT_CLK, addr);
+ tmp = getfrom_srom(addr);
+ sendto_srom(command, addr);
+
+ word = (word << 1) | ((tmp >> 3) & 0x01);
+ }
+
+ sendto_srom(command & 0x0000ff00, addr);
+
+ return word;
+}
+
+static void
+sendto_srom(u_int command, u_long addr)
+{
+ outl(command, addr);
+ udelay(1);
+
+ return;
+}
+
+static int
+getfrom_srom(u_long addr)
+{
+ s32 tmp;
+
+ tmp = inl(addr);
+ udelay(1);
+
+ return tmp;
+}
+
--- /dev/null
+#include <ppc_asm.tmpl>
+#include <mpc824x.h>
+
+ .globl __pci_config_read_32
+__pci_config_read_32:
+ lis r4, 0xfec0
+ stwbrx r3, r0, r4
+ sync
+ lis r4, 0xfee0
+ lwbrx r3, 0, r4
+ blr
+ .globl __pci_config_read_16
+__pci_config_read_16:
+ lis r4, 0xfec0
+ andi. r5, r3, 2
+ stwbrx r3, r0, r4
+ sync
+ oris r4, r5, 0xfee0
+ lhbrx r3, r0, r4
+ blr
+ .globl __pci_config_read_8
+__pci_config_read_8:
+ lis r4, 0xfec0
+ andi. r5, r3, 3
+ stwbrx r3, r0, r4
+ sync
+ oris r4, r5, 0xfee0
+ lbz r3, 0(4)
+ blr
+ .globl __pci_config_write_32
+__pci_config_write_32:
+ lis r5, 0xfec0
+ stwbrx r3, r0, r5
+ sync
+ lis r5, 0xfee0
+ stwbrx r4, r0, r5
+ sync
+ blr
+ .globl __pci_config_write_16
+__pci_config_write_16:
+ lis r5, 0xfec0
+ andi. r6, r3, 2
+ stwbrx r3, r0, 5
+ sync
+ oris r5, r6, 0xfee0
+ sthbrx r4, r0, r5
+ sync
+ blr
+ .globl __pci_config_write_8
+__pci_config_write_8:
+ lis r5, 0xfec0
+ andi. r6, r3, 3
+ stwbrx r3, r0, r5
+ sync
+ oris r5, r6, 0xfee0
+ stb r4, 0(r5)
+ sync
+ blr
+ .globl in_8
+in_8:
+ oris r3, r3, 0xfe00
+ lbz r3,0(r3)
+ blr
+ .globl in_16
+in_16:
+ oris r3, r3, 0xfe00
+ lhbrx r3, 0, r3
+ blr
+ .globl in_16_ne
+in_16_ne:
+ oris r3, r3, 0xfe00
+ lhzx r3, 0, r3
+ blr
+ .globl in_32
+in_32:
+ oris r3, r3, 0xfe00
+ lwbrx r3, 0, r3
+ blr
+ .globl out_8
+out_8:
+ oris r3, r3, 0xfe00
+ stb r4, 0(r3)
+ eieio
+ blr
+ .globl out_16
+out_16:
+ oris r3, r3, 0xfe00
+ sthbrx r4, 0, r3
+ eieio
+ blr
+ .globl out_16_ne
+out_16_ne:
+ oris r3, r3, 0xfe00
+ sth r4, 0(r3)
+ eieio
+ blr
+ .globl out_32
+out_32:
+ oris r3, r3, 0xfe00
+ stwbrx r4, 0, r3
+ eieio
+ blr
+ .globl read_8
+read_8:
+ lbz r3,0(r3)
+ blr
+ .globl read_16
+read_16:
+ lhbrx r3, 0, r3
+ blr
+ .globl read_32
+read_32:
+ lwbrx r3, 0, r3
+ blr
+ .globl read_32_ne
+read_32_ne:
+ lwz r3, 0(r3)
+ blr
+ .globl write_8
+write_8:
+ stb r4, 0(r3)
+ eieio
+ blr
+ .globl write_16
+write_16:
+ sthbrx r4, 0, r3
+ eieio
+ blr
+ .globl write_32
+write_32:
+ stwbrx r4, 0, r3
+ eieio
+ blr
+ .globl write_32_ne
+write_32_ne:
+ stw r4, 0(r3)
+ eieio
+ blr
+
+
+.globl early_init_f
+
+early_init_f:
+ mflr r11
+ lis r10, 0x8000
+
+ /* PCI Latency Timer */
+ li r4, 0x0d
+ ori r3, r10, PLTR@l
+ bl __pci_config_write_8
+
+ /* Cache Line Size */
+ li r4, 0x08
+ ori r3, r10, PCLSR@l
+ bl __pci_config_write_8
+
+ /* PCI Cmd */
+ li r4, 6
+ ori r3, r10, PCICR@l
+ bl __pci_config_write_16
+
+#if 1
+ /* PCI Stat */
+ ori r3, r10, PCISR@l
+ bl __pci_config_read_16
+ ori r4, r4, 0xffff
+ ori r3, r10, PCISR@l
+ bl __pci_config_write_16
+#endif
+
+ /* PICR1 */
+ lis r4, 0xff14
+ ori r4, r4, 0x1b98
+ ori r3, r10, PICR1@l
+ bl __pci_config_write_32
+
+
+ /* PICR2 */
+ lis r4, 0x0404
+ ori r4, r4, 0x0004
+ ori r3, r10, PICR2@l
+ bl __pci_config_write_32
+
+ /* MIOCR1 */
+ li r4, 0x00
+ ori r3, r10, MIOCR1@l
+ bl __pci_config_write_8
+
+ /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
+ /* SDRAM_CLK_DEL (0x77)*/
+ li r4, 0x10
+ ori r3, r10, MIOCR2@l
+ bl __pci_config_write_8
+
+ /* EUMBBAR */
+ lis r4, 0xfc00
+ ori r3, r10, EUMBBAR@l
+ bl __pci_config_write_32
+
+ /* AMBOR */
+
+ /* Even if Address Map B is not being used (though it should),
+ * the memory DLL needs to be cleared/set/cleared before using memory.
+ */
+
+ ori r3, r10, AMBOR@l
+ bl __pci_config_read_8 /* get Current bits */
+
+ andi. r4, r4, 0xffdf
+ ori r3, r10, AMBOR@l
+ bl __pci_config_write_16 /* Clear DLL_RESET */
+
+ ori r4, r4, 0x0020
+ ori r3, r10, AMBOR@l
+ bl __pci_config_write_16 /* Set DLL_RESET */
+
+ andi. r4, r4, 0xffdf
+ ori r3, r10, AMBOR@l
+ bl __pci_config_write_16 /* Clear DLL_RESET */
+
+ /* Preserve memgo bit */
+ /* MCCR1 */
+
+ lis r4, 0x75a8 // Safe Local ROM = 11+3 clocks
+// lis r4, 0x73a0 // Fast Local ROM = 7+3 clocks
+// oris r4, r4, 0x0010 // Burst ROM/Flash enable
+// oris r4, r4, 0x0004 // Self-refresh enable
+
+// ori r4,r4,0xFFFF // 16Mbit 2bank SDRAM
+// ori r4,r4,0xAAAA // 256Mbit 4bank SDRAM (8245 only)
+// ori r4,r4,0x5555 // 64Mbit 2bank SDRAM
+ ori r4,r4,0x0000 // 64Mbit 4bank SDRAM
+
+ ori r3, r10, MCCR1@l
+ bl __pci_config_write_32
+
+ /* MCCR2 */
+
+ lis r4,0x0000
+/* oris r4,r4,0x4000 // TS_WAIT_TIMER = 3 clocks */
+/* oris r4,r4,0x0400 // ASRISE = 2 clocks */
+/* oris r4,r4,0x0040 // ASFALL = 2 clocks */
+/* oris r4,r4,0x0010 // SDRAM Parity (else ECC) */
+/* oris r4,r4,0x0008 // Write parity check */
+/* oris r4,r4,0x0004 // SDRAM inline reads */
+
+
+/* Select a refresh rate; it needs to match the bus speed; if too */
+/* slow, data may be lost; if too fast, performance is lost. We */
+/* use the fastest value so we run at all speeds. */
+/* Refresh = (15600ns/busclk) - (213 (see UM)). */
+
+/* ori r4,r4,0x1d2c // 133 MHz mem bus = 1867 */
+ ori r4,r4,0x150c /* 100 MHz mem bus = 1347 */
+/* ori r4,r4,0x10fc // 83 MHz mem bus = 1087 */
+/* ori r4,r4,0x0cc4 // 66 MHz mem bus = 817 */
+/* ori r4,r4,0x04cc // 33 MHz mem bus (SAFE) = 307 */
+
+/* ori r4,r4,0x0002 // Reserve a page */
+/* ori r4,r4,0x0001 // RWM parity */
+
+ ori r3, r10, MCCR2@l
+ bl __pci_config_write_32
+
+
+ /* MCCR3 */
+ lis r4,0x7000 // BSTOPRE_M = 7 (see A/N)
+ oris r4,r4,0x0800 // REFREC = 8 clocks
+ ori r3, r10, MCCR3@l
+ bl __pci_config_write_32
+
+ /* MCCR4 */
+ lis r4, 0x3000 // PRETOACT = 3 clocks
+ oris r4,r4,0x0500 // ACTOPRE = 5 clocks
+ oris r4,r4,0x0080 // Enable 8-beat burst (32-bit bus)
+// oris r4,r4,0x0040 // Enable Inline ECC/Parity
+ oris r4,r4,0x0020 // EXTROM enabled
+ oris r4,r4,0x0010 // Registered buffers
+// oris r4,r4,0x0000 // BSTOPRE_U = 0 (see A/N)
+ oris r4,r4,0x0002 // DBUS_SIZ[2] (8 bit on RCS1)
+
+// ori r4,r4,0x8000 // Registered DIMMs
+ ori r4,r4,0x3000 // CAS Latency (CL=3) (see RDLAT)
+// ori r4,r4,0x2000 // CAS Latency (CL=2) (see RDLAT)
+// ori r4,r4,0x0300 // Sequential wrap/8-beat burst
+ ori r4,r4,0x0030 // ACTORW = 3 clocks
+ ori r4,r4,0x0009 // BSTOPRE_L = 9 (see A/N)
+
+ ori r3, r10, MCCR4@l
+ bl __pci_config_write_32
+
+ /* MSAR1 */
+ lis r4, 0xffffff00
+ ori r3, r10, MSAR1@l
+ bl __pci_config_write_32
+
+ /* MSAR2 */
+ lis r4, 0xffffffff
+ ori r3, r10, MSAR2@l
+ bl __pci_config_write_32
+
+ /* MESAR1 */
+ lis r4, 0x03030300@h
+ li r4, 0x03030300@l
+ ori r3, r10, EMSAR1@l
+ bl __pci_config_write_32
+
+ /* MESAR2 */
+ lis r4, 0x03030303@h
+ li r4, 0x03030303@l
+ ori r3, r10, EMSAR2@l
+ bl __pci_config_write_32
+
+ /* MEAR1 */
+ lis r4, 0xffffff7f@h
+ li r4, 0xffffff7f@l
+ ori r3, r10, MEAR1@l
+ bl __pci_config_write_32
+
+ /* MEAR2 */
+ lis r4, 0xffffffff@h
+ li r4, 0xffffffff@l
+ ori r3, r10, MEAR2@l
+ bl __pci_config_write_32
+
+ /* MEEAR1 */
+ lis r4, 0x03030300@h
+ li r4, 0x03030300@l
+ ori r3, r10, EMEAR1@l
+ bl __pci_config_write_32
+
+ /* MEEAR2 */
+ lis r4, 0x03030303@h
+ li r4, 0x03030303@l
+ ori r3, r10, EMEAR2@l
+ bl __pci_config_write_32
+
+ /* ODCR */
+ li r4, 0x1c
+ ori r3, r10, ODCR@l
+ bl __pci_config_write_8
+
+ /* MBER */
+ li r4, 0x01
+ ori r3, r10, MBER@l
+ bl __pci_config_write_8
+
+ /* Page CTR aka PGMAX */
+ li r4, 0x32
+ ori r3, r10, 0xa3
+ bl __pci_config_write_8
+
+#if 0
+ /* CLK Drive */
+ ori r4, r10, 0xfc01 /* Top bit will be ignored */
+ ori r3, r10, 0x74
+ bl __pci_config_write_16
+#endif
+
+ /* delay */
+ lis r7, 1
+ mtctr r7
+label1: bdnz label1
+
+ /* Set memgo bit */
+ /* MCCR1 */
+ ori r3, r10, MCCR1@l
+ bl __pci_config_read_32
+ lis r7, 0x0008
+ or r4, r3, r7
+ ori r3, r10, MCCR1@l
+ bl __pci_config_write_32
+
+ /* delay again */
+ lis r7, 1
+ mtctr r7
+label2: bdnz label2
+
+ mtlr r11
+ blr
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc824x.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, uchar *dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+
+/*
+ * don't ask. its stupid, but more than one soul has had to live with this mistake
+ * "swaptab[i]" is the value of "i" with the bits reversed.
+ */
+
+#define MUSENKI_BROKEN_FLASH 1
+
+#ifdef MUSENKI_BROKEN_FLASH
+unsigned char swaptab[256] = {
+ 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+ 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+ 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+ 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+ 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+ 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+ 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+ 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+ 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+ 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+ 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+ 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+ 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+ 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+ 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+ 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+ 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+ 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+ 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+ 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+ 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+ 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+ 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+ 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+ 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+ 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+ 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+ 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+ 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+ 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+ 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+ 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
+};
+
+#define BS(b) (swaptab[b])
+
+#else
+
+#define BS(b) (b)
+
+#endif
+
+#define BYTEME(x) ((x) & 0xFF)
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CFG_FLASH_BASE0_PRELIM);
+
+ size_b0 = flash_get_size((vu_char *)CFG_FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0: "
+ "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+ flash_info[0].flash_id,
+ size_b0, size_b0<<20);
+ }
+
+ DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CFG_FLASH_BASE1_PRELIM);
+ size_b1 = flash_get_size((vu_char *)CFG_FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE);
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ if (size_b1) {
+ flash_info[1].size = size_b1;
+ flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[1]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[1]);
+#endif
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ flash_info[1].size = 0;
+ }
+
+ DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+ return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += 0x00020000; /* 128k per bank */
+ }
+ return;
+
+ default:
+ printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
+ return;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("STM "); break;
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_MT: printf ("MT "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F320JA3: printf ("28F320JA3 (32Mbit = 128K x 32)\n");
+ break;
+ case FLASH_28F640JA3: printf ("28F640JA3 (64Mbit = 128K x 64)\n");
+ break;
+ case FLASH_28F128JA3: printf ("28F128JA3 (128Mbit = 128K x 128)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ if (info->size >= (1 << 20)) {
+ i = 20;
+ } else {
+ i = 10;
+ }
+ printf (" Size: %ld %cB in %d Sectors\n",
+ info->size >> i,
+ (i == 20) ? 'M' : 'k',
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+ vu_char manuf, device;
+
+ addr[0] = BS(0x90);
+ manuf = BS(addr[0]);
+ DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf);
+
+ switch (manuf) {
+ case BYTEME(AMD_MANUFACT):
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case BYTEME(FUJ_MANUFACT):
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case BYTEME(SST_MANUFACT):
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case BYTEME(STM_MANUFACT):
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case BYTEME(INTEL_MANUFACT):
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */
+ return 0; /* no or unknown flash */
+ }
+
+ device = BS(addr[2]); /* device ID */
+
+ DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device);
+
+ switch (device) {
+ case BYTEME(INTEL_ID_28F320JA3):
+ info->flash_id += FLASH_28F320JA3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case BYTEME(INTEL_ID_28F640JA3):
+ info->flash_id += FLASH_28F640JA3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case BYTEME(INTEL_ID_28F128JA3):
+ info->flash_id += FLASH_28F128JA3;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */
+ return 0; /* => no or unknown flash */
+
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = BS(0xFF); /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+ printf ("Can erase only Intel flash types - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_char *addr = (vu_char *)(info->start[sect]);
+ unsigned long status;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = BS(0x50); /* clear status register */
+ *addr = BS(0x20); /* erase setup */
+ *addr = BS(0xD0); /* erase confirm */
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = BS(0xB0); /* suspend erase */
+ *addr = BS(0xFF); /* reset to read mode */
+ return 1;
+ }
+
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ *addr = BS(0xFF); /* reset to read mode */
+ }
+ }
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define FLASH_WIDTH 1 /* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ uchar *wp = (uchar *)addr;
+ int rc;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+
+ while (cnt > 0) {
+ if ((rc = write_data(info, wp, *src)) != 0) {
+ return rc;
+ }
+ wp++;
+ src++;
+ cnt--;
+ }
+
+ return cnt;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, uchar *dest, uchar data)
+{
+ vu_char *addr = (vu_char *)dest;
+ ulong status;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((BS(*addr) & data) != data) {
+ return 2;
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = BS(0x40); /* write setup */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+
+ start = get_timer (0);
+
+ while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *addr = BS(0xFF); /* restore read mode */
+ return 1;
+ }
+ }
+
+ *addr = BS(0xFF); /* restore read mode */
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+
+ /* We have to clear the initial data area here. Couldn't have done it
+ * earlier because DRAM had not been initialized.
+ */
+int board_pre_init(void)
+{
+ memset((void *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET),
+ 0,
+ CFG_INIT_DATA_SIZE);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ ulong busfreq = get_bus_freq(0);
+ char buf[32];
+
+ printf("MUSENKI ");
+ printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+
+ return 0;
+}
+
+long int initdram(int board_type)
+{
+#if 0 /* FIXME */
+ int i, cnt;
+ volatile uchar * base = CFG_SDRAM_BASE;
+ volatile ulong * addr;
+ ulong save[32];
+ ulong val, ret = 0;
+
+ for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+ addr = (volatile ulong *)base + cnt;
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ addr = (volatile ulong *)base;
+ save[i] = *addr;
+ *addr = 0;
+
+ if (*addr != 0) {
+ *addr = save[i];
+ goto Done;
+ }
+
+ for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+ addr = (volatile ulong *)base + cnt;
+ val = *addr;
+ *addr = save[--i];
+ if (val != ~cnt) {
+ ulong new_bank0_end = cnt * sizeof(long) - 1;
+ ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
+ ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ ret = cnt * sizeof(long);
+ goto Done;
+ }
+ }
+
+ ret = CFG_MAX_RAM_SIZE;
+Done:
+ return ret;
+#else
+ return (32 * 1024 * 1024);
+#endif
+}
--- /dev/null
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/ppc/boot/ns16550.c)
+ * modified to use CFG_ISA_MEM and new defines
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+typedef struct NS16550 *NS16550_t;
+
+const NS16550_t COM_PORTS[] = { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600)};
+
+volatile struct NS16550 *
+NS16550_init(int chan, int baud_divisor)
+{
+ volatile struct NS16550 *com_port;
+ com_port = (struct NS16550 *) COM_PORTS[chan];
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE; /* Access baud rate */
+ com_port->dll = baud_divisor & 0xff; /* 9600 baud */
+ com_port->dlm = (baud_divisor >> 8) & 0xff;
+ com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
+ com_port->mcr = MCR_RTS; /* RTS/DTR */
+ com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
+return (com_port);
+}
+
+void
+NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor)
+{
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE; /* Access baud rate */
+ com_port->dll = baud_divisor & 0xff; /* 9600 baud */
+ com_port->dlm = (baud_divisor >> 8) & 0xff;
+ com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
+ com_port->mcr = MCR_RTS; /* RTS/DTR */
+ com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
+}
+
+void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
+{
+ while ((com_port->lsr & LSR_THRE) == 0) ;
+ com_port->thr = c;
+}
+
+unsigned char
+NS16550_getc(volatile struct NS16550 *com_port)
+{
+ while ((com_port->lsr & LSR_DR) == 0) ;
+ return (com_port->rbr);
+}
+
+int NS16550_tstc(volatile struct NS16550 *com_port)
+{
+ return ((com_port->lsr & LSR_DR) != 0);
+}
+
+
+
--- /dev/null
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/ppc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CFG_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ * further modified to support the 8245 duart
+ * modifications (c) Paul Jimenez, Musenki, Inc. 2001.
+ */
+
+
+struct NS16550
+ {
+ unsigned char rbrthrdlb; /* 0 */
+ unsigned char ierdmb; /* 1 */
+ unsigned char iirfcrafr; /* 2 */
+ unsigned char lcr; /* 3 */
+ unsigned char mcr; /* 4 */
+ unsigned char lsr; /* 5 */
+ unsigned char msr; /* 6 */
+ unsigned char scr; /* 7 */
+ unsigned char reserved[2]; /* 8 & 9 */
+ unsigned char dsr; /* 10 */
+ unsigned char dcr; /* 11 */
+ };
+
+
+#define rbr rbrthrdlb
+#define thr rbrthrdlb
+#define dll rbrthrdlb
+#define ier ierdmb
+#define dlm ierdmb
+#define iir iirfcrafr
+#define fcr iirfcrafr
+#define afr iirfcrafr
+
+#define FCR_FIFO_EN 0x01 /*fifo enable*/
+#define FCR_RXSR 0x02 /*reciever soft reset*/
+#define FCR_TXSR 0x04 /*transmitter soft reset*/
+#define FCR_DMS 0x08 /* DMA Mode Select */
+
+#define MCR_RTS 0x02 /* Readyu to Send */
+#define MCR_LOOP 0x10 /* Local loopback mode enable */
+/* #define MCR_DTR 0x01 noton 8245 duart */
+/* #define MCR_DMA_EN 0x04 noton 8245 duart */
+/* #define MCR_TX_DFR 0x08 noton 8245 duart */
+
+#define LCR_WLS_MSK 0x03 /* character length slect mask*/
+#define LCR_WLS_5 0x00 /* 5 bit character length */
+#define LCR_WLS_6 0x01 /* 6 bit character length */
+#define LCR_WLS_7 0x02 /* 7 bit character length */
+#define LCR_WLS_8 0x03 /* 8 bit character length */
+#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN 0x08 /* Parity eneble*/
+#define LCR_EPS 0x10 /* Even Parity Select*/
+#define LCR_STKP 0x20 /* Stick Parity*/
+#define LCR_SBRK 0x40 /* Set Break*/
+#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
+
+#define LSR_DR 0x01 /* Data ready */
+#define LSR_OE 0x02 /* Overrun */
+#define LSR_PE 0x04 /* Parity error */
+#define LSR_FE 0x08 /* Framing error */
+#define LSR_BI 0x10 /* Break */
+#define LSR_THRE 0x20 /* Xmit holding register empty */
+#define LSR_TEMT 0x40 /* Xmitter empty */
+#define LSR_ERR 0x80 /* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1 0x03
+
+
+volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
+void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc(volatile struct NS16550 *com_port);
+int NS16550_tstc(volatile struct NS16550 *com_port);
+void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc824x/start.o (.text)
+ common/board.o (.text)
+ ppc/ppcstring.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include "ns16550.h"
+
+#if CONFIG_CONS_INDEX == 1
+static struct NS16550 *console = (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
+#elif CONFIG_CONS_INDEX == 2
+static struct NS16550 *console = (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
+#else
+#error no valid console defined
+#endif
+
+void
+serial_init (unsigned long dummy, int baudrate)
+{
+ int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate;
+
+ NS16550_init(CONFIG_CONS_INDEX - 1, clock_divisor);
+}
+
+void
+serial_putc(const char c)
+{
+ if (c == '\n')
+ {
+ serial_putc ('\r');
+ }
+ NS16550_putc(console, c);
+}
+
+void
+serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+
+int
+serial_getc(void)
+{
+ return NS16550_getc(console);
+}
+
+int
+serial_tstc(void)
+{
+ return NS16550_tstc(console);
+}
+
+void
+serial_setbrg (unsigned long dummy, int baudrate)
+{
+ int clock_divisor = CFG_SERIAL_CLOCK / 16 / baudrate;
+
+ NS16550_reinit(console, clock_divisor);
+}
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+
+ulong get_bus_freq(ulong ignore)
+{
+ return 100000000;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Measure CPU clock speed
+ */
+
+/* Table to convert pllratio to actual processor clock scaling factor (*10)
+ */
+#ifdef CONFIG_MPC8245 /* FIXME */
+short pllratio_to_factor[] = {
+ 00, 00, 00, 10, 20, 20, 25, 00, 00, 00, 00, 00, 00, 00, 00, 00,
+ 00, 00, 00, 10, 00, 00, 00, 45, 30, 00, 40, 00, 00, 00, 35, 00,
+};
+#endif
+
+ulong get_gclk_freq(void)
+{
+ uint hid1 = mfspr(HID1);
+
+ /* 5 bits for PLL ration on 8240/8245 */
+ hid1 = (hid1 >> (32-5)) & 0x1f;
+
+ return (pllratio_to_factor[hid1] * get_bus_freq(0)) / 10;
+}
+
+/* ------------------------------------------------------------------------- */
+
/* return total ram size */
return (CFG_SDRAM0_SIZE * 1024 * 1024);
}
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+void misc_init_r(bd_t *bd)
+{
+#ifdef CFG_LED_BASE
+ uchar ds = *(unsigned char *)(CFG_LED_BASE + 1);
+ uchar ss;
+ uchar tmp[64];
+ int res;
+ if((ds != 0) && (ds != 0xff)) {
+ res = getenv_r("ethaddr", tmp, sizeof(tmp));
+ if(res > 0) {
+ ss = ((ds >> 4) & 0x0f);
+ ss += ss < 0x0a?'0':('a'- 10);
+ tmp[15] = ss;
+
+ ss = (ds & 0x0f);
+ ss += ss < 0x0a?'0':('a'- 10);
+ tmp[16] = ss;
+
+ tmp[17] = '\0';
+ setenv("ethaddr", tmp);
+ /* set the led to show the address */
+ *((unsigned char *)(CFG_LED_BASE + 1)) = ds;
+ }
+ }
+#endif /* CFG_LED_BASE */
+}
+#endif /* CONFIG_MISC_INIT_R */
#include <w83c553f.h>
#endif
-#undef DEBUG
-
static char *failed = "*** failed ***\n";
#ifdef CONFIG_PCU_E
}
#if defined(CONFIG_WATCHDOG)
- puts (" Watchdog enabled\n");
-#endif /* CONFIG_WATCHDOG */
+ puts (" Watchdog enabled\n");
WATCHDOG_RESET();
+#endif /* CONFIG_WATCHDOG */
puts ("Board: "); /* Check Board */
int i;
char buf[32];
+#ifdef DEBUG
+ print_num ("bd address", (ulong)bd );
+#endif
print_num ("memstart", bd->bi_memstart );
print_num ("memsize", bd->bi_memsize );
print_num ("flashstart", bd->bi_flashstart );
static void print_num(const char *name, ulong value)
{
- printf ("%-12s= 0x%08lx\n", name, value);
+ printf ("%-12s= 0x%08lX\n", name, value);
}
static void print_str(const char *name, const char *str)
unsigned long get_tbclk (void)
{
ulong tbclk;
+
+#if defined(CONFIG_MPC8245)
+ tbclk = (CONFIG_SYS_CLK_FREQ + 3L) / 4L;
+#elif defined(CONFIG_CU824);
+ tbclk = CONFIG_SYS_CLK_FREQ;
+#else
/* Pointer to initial global data area */
-#ifndef CONFIG_CU824
init_data_t *idata =
(init_data_t *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
tbclk = (idata->cpu_clk + 3L) / 4L;
-#else
- tbclk = CONFIG_SYS_CLK_FREQ;
#endif
-
return (tbclk);
}
void
cpu_init_f (void)
{
-/* MOUSSE and SANDPOINT boards initialized in asm */
-#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_SANDPOINT)
+/* MOUSSE, MUSENKI and SANDPOINT boards initialized in asm */
+#if (!defined(CONFIG_MOUSSE) && \
+ !defined(CONFIG_MUSENKI) && \
+ !defined(CONFIG_SANDPOINT) )
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
#endif
in_flash:
-#if defined(CONFIG_SANDPOINT)
+#if defined(CONFIG_SANDPOINT) || defined(CONFIG_MUSENKI)
bl early_init_f /* must be ASM: no stack yet! */
#endif
/*
* Setup BATs - cannot be done in C since we don't have a stack yet
*/
- bl setup_bats
+ bl setup_bats
/* Enable MMU.
*/
ori r3, r3, (MSR_IR | MSR_DR)
mtmsr r3
+#ifndef CONFIG_MUSENKI
/* Enable and invalidate data cache.
*/
mfspr r3, HID0
sync
mtspr 1011, r3
+#endif /* CONFIG_MUSENKI */
/*
* Thisk the stack pointer *somewhere* sensible. Doesnt
/* 24.21 - (26): Initialize DSR */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
- /* 24.21 - (27): Initialize PSMR2 */
+ /* 24.21 - (27): Initialize PSMR2
*
* Settings:
* CRC = 32-Bit CCITT
#if defined(CONFIG_WATCHDOG) || defined(CFG_CMA_LCD_HEARTBEAT)
- if ((timestamp % 1000) == 0) {
+ /*
+ * The shortest watchdog period of all boards is (so far)
+ * approx. 1 sec, thus re-trigger watchdog at least
+ * every 500 ms = CFG_HZ / 2
+ */
+ if ((timestamp % (CFG_HZ / 2)) == 0) {
#if defined(CFG_CMA_LCD_HEARTBEAT)
extern void lcd_heartbeat(void);
lcd_heartbeat();
}
/****************************************************************************/
-
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
#define CONFIG_BOOTDELAY 5
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DHCP | \
+ 0/* CFG_CMD_DATE */ )
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
#undef CONFIG_WATCHDOG /* watchdog disabled */
+/* ATA / IDE and partition support */
+#define CONFIG_MAC_PARTITION 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_ISO_PARTITION 1
+#undef CONFIG_ATAPI
+#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
+#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
/* choose SCC1 ethernet (10BASET on motherboard)
* or FEC ethernet (10/100 on daughterboard)
*/
#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif
+/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */
+#define CFG_PCMCIA_MEM_ADDR (0x50000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0x54000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0x5C000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+/* we have 8 windows, we take everything up to 60000000 */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0000
+/*#define CFG_ATA_ALT_OFFSET 0x0100 */
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the CU824 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824x 1
+#define CONFIG_MPC8245 1
+#define CONFIG_MUSENKI 1
+
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_COMMANDS CONFIG_CMD_DFL
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS 8 /* Max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+
+#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
+
+/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
+ * reset vector is actually located at FFB00100, but the 8245
+ * takes care of us.
+ */
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_EUMB_ADDR 0xFC000000
+
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
+
+ /* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+#if 0
+/* Size in bytes reserved for initial data */
+#define CFG_INIT_DATA_SIZE 128
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END 0x1000000 /* 16MB */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+#else
+#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CFG_SERIAL_CLOCK CONFIG_SYS_CLK_FREQ
+#define CFG_HZ 1000
+
+#define CFG_ETH_DEV_FN 0x7800
+#define CFG_ETH_IOBASE 0x00104000
+
+ /* Bit-field values for MCCR1.
+ */
+#define CFG_ROMNAL 0xf
+#define CFG_ROMFAL 0x1f
+#define CFG_DBUS_SIZE 0x3
+
+ /* Bit-field values for MCCR2.
+ */
+#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
+#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
+
+ /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CFG_BSTOPRE 0 /* FIXME: was 192 */
+
+ /* Bit-field values for MCCR3.
+ */
+#define CFG_REFREC 2 /* Refresh to activate interval */
+
+ /* Bit-field values for MCCR4.
+ */
+#define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
+#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
+#define CFG_ACTORW 0xa /* FIXME was 2 */
+#define CFG_REGISTERD_TYPE_BUFFER 1
+
+#define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+
+#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x3ff00000
+#define CFG_BANK1_END 0x3fffffff
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x3ff00000
+#define CFG_BANK4_END 0x3fffffff
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x3ff00000
+#define CFG_BANK5_END 0x3fffffff
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x3ff00000
+#define CFG_BANK6_END 0x3fffffff
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x3ff00000
+#define CFG_BANK7_END 0x3fffffff
+#define CFG_BANK7_ENABLE 0
+
+#define CFG_ODCR 0xff
+
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#if 0
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#else
+/* this is just invalid */
+#define CFG_IBAT1L (0x3ff00000 | BATL_PP_00 | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U (0x3ff00000 | BATU_BL_128K )
+#endif
+
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+
+ /* Warining: environment is not EMBEDDED in the ppcboot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFF800000 /* right at the start of flash */
+#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
+#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
+#define CFG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+#endif /* __CONFIG_H */
#define CONFIG_8xx_CONS_SCC2
#endif
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#if 0
+#if 1
#define CONFIG_WATCHDOG 1 /* watchdog enabled */
#endif
/* Ethernet MAC address */
#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
+/*
+ * Define this to set the last octet of the ethernet address from the
+ * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
+ * switch and the LEDs are backwards with respect to each other. DS7
+ * is on the board edge side of both the LED strip and the DS0-DS7
+ * switch.
+ */
+#if 0
+# define CONFIG_MISC_INIT_R
+#endif
+
/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
CFG_CMD_I2C | \
CFG_CMD_REGINFO | \
CFG_CMD_IMMAP | \
- CFG_CMD_MII)
+#ifdef CONFIG_ETHER_USE_FCC2
+ CFG_CMD_MII | \
+#endif
+ 0 )
/* Where do the internal registers live? */
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef __IMAGE_H__
+#ifndef __IMAGE_H__
#define __IMAGE_H__
/*
* Operating System Codes
*/
-#define IH_OS_INVALID 0 /* Invalid OS */
-#define IH_OS_OPENBSD 1 /* OpenBSD */
-#define IH_OS_NETBSD 2 /* NetBSD */
-#define IH_OS_FREEBSD 3 /* FreeBSD */
-#define IH_OS_4_4BSD 4 /* 4.4BSD */
-#define IH_OS_LINUX 5 /* Linux */
-#define IH_OS_SVR4 6 /* SVR4 */
-#define IH_OS_ESIX 7 /* Esix */
-#define IH_OS_SOLARIS 8 /* Solaris */
-#define IH_OS_IRIX 9 /* Irix */
-#define IH_OS_SCO 10 /* SCO */
-#define IH_OS_DELL 11 /* Dell */
-#define IH_OS_NCR 12 /* NCR */
-#define IH_OS_LYNXOS 13 /* LynxOS */
-#define IH_OS_VXWORKS 14 /* VxWorks */
-#define IH_OS_PSOS 15 /* pSOS */
-#define IH_OS_QNX 16 /* QNX */
-#define IH_OS_PPCBOOT 17 /* Firmware */
+#define IH_OS_INVALID 0 /* Invalid OS */
+#define IH_OS_OPENBSD 1 /* OpenBSD */
+#define IH_OS_NETBSD 2 /* NetBSD */
+#define IH_OS_FREEBSD 3 /* FreeBSD */
+#define IH_OS_4_4BSD 4 /* 4.4BSD */
+#define IH_OS_LINUX 5 /* Linux */
+#define IH_OS_SVR4 6 /* SVR4 */
+#define IH_OS_ESIX 7 /* Esix */
+#define IH_OS_SOLARIS 8 /* Solaris */
+#define IH_OS_IRIX 9 /* Irix */
+#define IH_OS_SCO 10 /* SCO */
+#define IH_OS_DELL 11 /* Dell */
+#define IH_OS_NCR 12 /* NCR */
+#define IH_OS_LYNXOS 13 /* LynxOS */
+#define IH_OS_VXWORKS 14 /* VxWorks */
+#define IH_OS_PSOS 15 /* pSOS */
+#define IH_OS_QNX 16 /* QNX */
+#define IH_OS_PPCBOOT 17 /* Firmware */
/*
* CPU Architecture Codes (supported by Linux)
*/
-#define IH_CPU_INVALID 0 /* Invalid CPU */
-#define IH_CPU_ALPHA 1 /* Alpha */
-#define IH_CPU_ARM 2 /* ARM */
-#define IH_CPU_I386 3 /* Intel x86 */
-#define IH_CPU_IA64 4 /* IA64 */
-#define IH_CPU_MIPS 5 /* MIPS */
-#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */
-#define IH_CPU_PPC 7 /* PowerPC */
-#define IH_CPU_S390 8 /* IBM S390 */
-#define IH_CPU_SH 9 /* SuperH */
-#define IH_CPU_SPARC 10 /* Sparc */
-#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
+#define IH_CPU_INVALID 0 /* Invalid CPU */
+#define IH_CPU_ALPHA 1 /* Alpha */
+#define IH_CPU_ARM 2 /* ARM */
+#define IH_CPU_I386 3 /* Intel x86 */
+#define IH_CPU_IA64 4 /* IA64 */
+#define IH_CPU_MIPS 5 /* MIPS */
+#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */
+#define IH_CPU_PPC 7 /* PowerPC */
+#define IH_CPU_S390 8 /* IBM S390 */
+#define IH_CPU_SH 9 /* SuperH */
+#define IH_CPU_SPARC 10 /* Sparc */
+#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
/*
* Image Types
* Immediately after the terminating 0 follow the images, one by
* one, all aligned on "uint32_t" boundaries (size rounded up to
* a multiple of 4 bytes).
+ *
+ * "Firmware Images" are binary images containing firmware (like
+ * PPCBoot or FPGA images) which usually will be programmed to
+ * flash memory.
+ *
+ * "Script files" are command sequences that will be executed by
+ * PPCBoot's command interpreter; this feature is especially
+ * useful when you configure PPCBoot to use a real shell (hush)
+ * as command interpreter.
*/
-#define IH_TYPE_INVALID 0 /* Invalid Image */
+#define IH_TYPE_INVALID 0 /* Invalid Image */
#define IH_TYPE_STANDALONE 1 /* Standalone Program */
#define IH_TYPE_KERNEL 2 /* OS Kernel Image */
#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */
#define IH_TYPE_MULTI 4 /* Multi-File Image */
-#define IH_TYPE_FIRMWARE 5 /* Binary Image to be programmed in the flash */
-#define IH_TYPE_SCRIPT 6 /* Script file to be executed from memory */
+#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
+#define IH_TYPE_SCRIPT 6 /* Script file */
/*
* Compression Types
*/
-#define IH_COMP_NONE 0 /* No Compression Used */
-#define IH_COMP_GZIP 1 /* gzip Compression Used */
+#define IH_COMP_NONE 0 /* No Compression Used */
+#define IH_COMP_GZIP 1 /* gzip Compression Used */
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
-#define IH_MAGIC 0x27051956 /* Image Magic Number */
-#define IH_NMLEN 32 /* Image Name Length */
+#define IH_MAGIC 0x27051956 /* Image Magic Number */
+#define IH_NMLEN 32 /* Image Name Length */
/*
* all data in network byte order (aka natural aka bigendian)
uint32_t ih_hcrc; /* Image Header CRC Checksum */
uint32_t ih_time; /* Image Creation Timestamp */
uint32_t ih_size; /* Image Data Size */
- uint32_t ih_load; /* Data Load Address */
+ uint32_t ih_load; /* Data Load Address */
uint32_t ih_ep; /* Entry Point Address */
uint32_t ih_dcrc; /* Image Data CRC Checksum */
uint8_t ih_os; /* Operating System */
*/
-#if DEBUG
+#ifdef DEBUG
/* #include <assert.h> */
#define assert(x) ((void)0)
#else
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#include <config.h>
/* CPU Types */
-#define CPU_TYPE_601 0x01 /* PPC 601 CPU */
-#define CPU_TYPE_602 0x02 /* PPC 602 CPU */
-#define CPU_TYPE_603 0x03 /* PPC 603 CPU */
-#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */
-#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */
-#define CPU_TYPE_604 0x04 /* PPC 604 CPU */
-#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */
-#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */
-#define CPU_TYPE_750 0x08 /* PPC 750 CPU */
-#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */
-#define CPU_TYPE_8245 0x8081 /* PPC 8245 CPU */
-#define _CACHE_ALIGN_SIZE 32 /* cache line size */
-
-/* spr976 - DMISS data tlb miss address register
- * spr977 - DCMP data tlb miss compare register
+#define CPU_TYPE_601 0x01 /* PPC 601 CPU */
+#define CPU_TYPE_602 0x02 /* PPC 602 CPU */
+#define CPU_TYPE_603 0x03 /* PPC 603 CPU */
+#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */
+#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */
+#define CPU_TYPE_604 0x04 /* PPC 604 CPU */
+#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */
+#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */
+#define CPU_TYPE_750 0x08 /* PPC 750 CPU */
+#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */
+#define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */
+#define _CACHE_ALIGN_SIZE 32 /* cache line size */
+
+/* spr976 - DMISS data tlb miss address register
+ * spr977 - DCMP data tlb miss compare register
* spr978 - HASH1 PTEG1 address register
* spr980 - HASH2 PTEG2 address register
* IMISS - instruction tlb miss address register
#if defined(CFG_ADDR_MAP_A)
#define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
-#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
+#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
#define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
-#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
+#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
#else /* Assume Map B, default */
#define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
-#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
+#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
#define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
-#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
+#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
#endif
#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
__asm__ ( \
" stwbrx %1, 0, %2\n \
sync\n \
- lbz %0, %4(%3)\n \
+ lbz %0, %4(%3)\n \
sync " \
: "=r" (reg) \
: "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
#define PMCR2 0x80000072 /* Power management config. 2 */
#define ODCR 0x80000073 /* Output Driver Control Register */
#define CLKDCR 0x80000074 /* CLK Driver Control Register */
-#ifdef CONFIG_MPC8245
+#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
#endif
#define PICR1_ST_GATH_EN 0x00000040
#if defined(CONFIG_MPC8240)
#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
-#elif defined(CONFIG_MPC8241) || defined(CONFIG_MPC8245)
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */
-#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */
+#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define MCCR1_SREN 0x00040000
#if defined(CONFIG_MPC8240)
#define MCCR1_RAM_TYPE 0x00020000
-#elif defined(CONFIG_MPC8245)
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MCCR1_SDRAM_EN 0x00020000
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#define MCCR3_RCD2_SHIFT 3
#define MCCR3_RP1_MSK 0x00000007
#define MCCR3_RP1_SHIFT 0
-#endif
+#endif
#define MCCR4_PRETOACT_MSK 0xf0000000
#define MCCR4_PRETOACT_SHIFT 28
#define MCCR4_INLINE 0x00400000
#if defined(CONFIG_MPC8240)
#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/
-#elif defined(CONFIG_MPC8245)
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#define BATL_PP_10 0x00000002 /* Read-write */
#define BATL_PP_11 0x00000003
-/* I'd attempt to do defines for the PP bits, but it's use is a bit too complex,
- * see the PowerPC Operating Environment Architecture section in the PowerPc arch book.
- * chapter 4
+/*
+ * I'd attempt to do defines for the PP bits, but it's use is a bit
+ * too complex, see the PowerPC Operating Environment Architecture
+ * section in the PowerPc arch book, chapter 4.
*/
/*eumb and epic config*/
#define EPIC_SVR 0x000410E0
#define EPIC_TFRR 0x000410F0
-/*note the information for these is rather mangled in the 8240 manual. these are guesses*/
+/*
+ * Note the information for these is rather mangled in the 8240 manual.
+ * These are guesses.
+ */
+
#define EPIC_GTCCR0 0x00041100
#define EPIC_GTCCR1 0x00041140
#define EPIC_GTCCR2 0x00041180
typedef unsigned char uchar;
typedef volatile unsigned long vu_long;
typedef volatile unsigned short vu_short;
+typedef volatile unsigned char vu_char;
#include "config.h"
#include <linux/bitops.h>
void prt_8260_clks (void);
#elif defined(CONFIG_4xx) || \
defined(CONFIG_8xx) || \
+ defined(CONFIG_BAB750) || \
defined(CONFIG_CU824) || \
defined(CONFIG_EVB64260) || \
defined(CONFIG_IOP480) || \
defined(CONFIG_MOUSSE) || \
- defined(CONFIG_BAB750) || \
+ defined(CONFIG_MUSENKI) || \
defined(CONFIG_SANDPOINT)
ulong get_gclk_freq (void);
ulong get_OPB_freq (void);
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "PPCBoot 1.1.2"
+#define PPCBOOT_VERSION "PPCBoot 1.1.3"
#endif /* __VERSION_H__ */
projects / users / rw / ppcboot.git / commitdiff