drm/amd/display: Update DCN10 resource

Update DCN10 to use legacy fast update and ensure that the MPCC count is
the same as the pipe_count.

Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 81fa2ac781f9fc7dc4bcf842b5a2c0a1f42954fc..563c5eec83ff3ddc768ab939abf8cacabc9ff590 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -569,6 +569,7 @@ static const struct dc_debug_options debug_defaults_diags = {
                .disable_pplib_clock_request = true,
                .disable_pplib_wm_range = true,
                .underflow_assert_delay_us = 0xFFFFFFFF,
+               .enable_legacy_fast_update = true,
 };
 
 static void dcn10_dpp_destroy(struct dpp **dpp)
@@ -1631,6 +1632,7 @@ static bool dcn10_resource_construct(
        /* valid pipe num */
        pool->base.pipe_count = j;
        pool->base.timing_generator_count = j;
+       pool->base.mpcc_count = j;
 
        /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
         * the value may be changed