mtd: rawnand: better name for the controller structure

In the raw NAND core, a NAND chip is described by a nand_chip structure,
while a NAND controller is described with a nand_hw_control structure
which is not very meaningful.

Rename this structure nand_controller.

As the structure gets renamed, it is logical to also rename the core
function initializing it from nand_hw_control_init() to
nand_controller_init().

Lastly, the 'hwcontrol' entry of the nand_chip structure is not
meaningful neither while it has the role of fallback when no controller
structure is provided by the driver (the controller driver is dumb and
can only control a single chip). Thus, it is renamed dummy_controller.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>

diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 30dae4c9d439edbfd4ccfc2e7e8112a9144922f9..855cc7729c436f76c3b11385a0ea854c7930f56f 100644 (file)
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -216,7 +216,7 @@ struct atmel_nand_controller_caps {
 };
 
 struct atmel_nand_controller {
-       struct nand_hw_control base;
+       struct nand_controller base;
        const struct atmel_nand_controller_caps *caps;
        struct device *dev;
        struct regmap *smc;
@@ -227,7 +227,7 @@ struct atmel_nand_controller {
 };
 
 static inline struct atmel_nand_controller *
-to_nand_controller(struct nand_hw_control *ctl)
+to_nand_controller(struct nand_controller *ctl)
 {
        return container_of(ctl, struct atmel_nand_controller, base);
 }
@@ -239,7 +239,7 @@ struct atmel_smc_nand_controller {
 };
 
 static inline struct atmel_smc_nand_controller *
-to_smc_nand_controller(struct nand_hw_control *ctl)
+to_smc_nand_controller(struct nand_controller *ctl)
 {
        return container_of(to_nand_controller(ctl),
                            struct atmel_smc_nand_controller, base);
@@ -263,7 +263,7 @@ struct atmel_hsmc_nand_controller {
 };
 
 static inline struct atmel_hsmc_nand_controller *
-to_hsmc_nand_controller(struct nand_hw_control *ctl)
+to_hsmc_nand_controller(struct nand_controller *ctl)
 {
        return container_of(to_nand_controller(ctl),
                            struct atmel_hsmc_nand_controller, base);
@@ -1966,7 +1966,7 @@ static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
        struct device_node *np = dev->of_node;
        int ret;
 
-       nand_hw_control_init(&nc->base);
+       nand_controller_init(&nc->base);
        INIT_LIST_HEAD(&nc->chips);
        nc->dev = dev;
        nc->caps = caps;

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 1306aaa7a8bfc4e463e226df053897ef107223cb..2e5efa0f9ea222e50c8c22727b1fcc62511b4940 100644 (file)
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -114,7 +114,7 @@ enum {
 
 struct brcmnand_controller {
        struct device           *dev;
-       struct nand_hw_control  controller;
+       struct nand_controller  controller;
        void __iomem            *nand_base;
        void __iomem            *nand_fc; /* flash cache */
        void __iomem            *flash_dma_base;
@@ -2433,7 +2433,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 
        init_completion(&ctrl->done);
        init_completion(&ctrl->dma_done);
-       nand_hw_control_init(&ctrl->controller);
+       nand_controller_init(&ctrl->controller);
        INIT_LIST_HEAD(&ctrl->host_list);
 
        /* NAND register range */

diff --git a/drivers/mtd/nand/raw/docg4.c b/drivers/mtd/nand/raw/docg4.c
index bb96cb33cd6b6cfbd10fe36afb97ef6862c187e7..4dccdfba61408ff643d3ec603dab7e2e3c091026 100644 (file)
--- a/drivers/mtd/nand/raw/docg4.c
+++ b/drivers/mtd/nand/raw/docg4.c
@@ -1257,8 +1257,8 @@ static void __init init_mtd_structs(struct mtd_info *mtd)
        nand->ecc.strength = DOCG4_T;
        nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
        nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
-       nand->controller = &nand->hwcontrol;
-       nand_hw_control_init(nand->controller);
+       nand->controller = &nand->dummy_controller;
+       nand_controller_init(nand->controller);
 
        /* methods */
        nand->cmdfunc = docg4_command;

diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index 51f0b340bc0df3371815fbf644984d9b07b03d1f..0aa54a949653b4f10333db0dae33699a9e9cbb67 100644 (file)
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -61,7 +61,7 @@ struct fsl_elbc_mtd {
 /* Freescale eLBC FCM controller information */
 
 struct fsl_elbc_fcm_ctrl {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct fsl_elbc_mtd *chips[MAX_BANKS];
 
        u8 __iomem *addr;        /* Address of assigned FCM buffer        */
@@ -879,7 +879,7 @@ static int fsl_elbc_nand_probe(struct platform_device *pdev)
                }
                elbc_fcm_ctrl->counter++;
 
-               nand_hw_control_init(&elbc_fcm_ctrl->controller);
+               nand_controller_init(&elbc_fcm_ctrl->controller);
                fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
        } else {
                elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;

diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index 75d3c951f61ad98777e6cd32886ff971cd5d4fac..96130d91e32cc86f0c992421635c216f0647afb6 100644 (file)
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -51,7 +51,7 @@ struct fsl_ifc_mtd {
 
 /* overview of the fsl ifc controller */
 struct fsl_ifc_nand_ctrl {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
 
        void __iomem *addr;     /* Address of assigned IFC buffer       */
@@ -1004,7 +1004,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
                ifc_nand_ctrl->addr = NULL;
                fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
 
-               nand_hw_control_init(&ifc_nand_ctrl->controller);
+               nand_controller_init(&ifc_nand_ctrl->controller);
        } else {
                ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
        }

diff --git a/drivers/mtd/nand/raw/jz4780_nand.c b/drivers/mtd/nand/raw/jz4780_nand.c
index e69f6ae4c53952f0c8d6798c9c0dda5e49057f06..49841dad347cc82ac6fe3a82b84e6d8feda1cce7 100644 (file)
--- a/drivers/mtd/nand/raw/jz4780_nand.c
+++ b/drivers/mtd/nand/raw/jz4780_nand.c
@@ -44,7 +44,7 @@ struct jz4780_nand_cs {
 struct jz4780_nand_controller {
        struct device *dev;
        struct jz4780_bch *bch;
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        unsigned int num_banks;
        struct list_head chips;
        int selected;
@@ -65,7 +65,8 @@ static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd)
        return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip);
 }
 
-static inline struct jz4780_nand_controller *to_jz4780_nand_controller(struct nand_hw_control *ctrl)
+static inline struct jz4780_nand_controller
+*to_jz4780_nand_controller(struct nand_controller *ctrl)
 {
        return container_of(ctrl, struct jz4780_nand_controller, controller);
 }
@@ -368,7 +369,7 @@ static int jz4780_nand_probe(struct platform_device *pdev)
        nfc->dev = dev;
        nfc->num_banks = num_banks;
 
-       nand_hw_control_init(&nfc->controller);
+       nand_controller_init(&nfc->controller);
        INIT_LIST_HEAD(&nfc->chips);
 
        ret = jz4780_nand_init_chips(nfc, pdev);

diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index 80a074cccb8227b798da8493298d1cfa9bf6243e..bd5f9a4b7b1620eb009ecd3c347ab43ecbbfdaaa 100644 (file)
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -318,7 +318,7 @@ struct marvell_nfc_caps {
  * @dma_buf:           32-bit aligned buffer for DMA transfers (NFCv1 only)
  */
 struct marvell_nfc {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct device *dev;
        void __iomem *regs;
        struct clk *core_clk;
@@ -335,7 +335,7 @@ struct marvell_nfc {
        u8 *dma_buf;
 };
 
-static inline struct marvell_nfc *to_marvell_nfc(struct nand_hw_control *ctrl)
+static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl)
 {
        return container_of(ctrl, struct marvell_nfc, controller);
 }
@@ -2745,7 +2745,7 @@ static int marvell_nfc_probe(struct platform_device *pdev)
                return -ENOMEM;
 
        nfc->dev = dev;
-       nand_hw_control_init(&nfc->controller);
+       nand_controller_init(&nfc->controller);
        INIT_LIST_HEAD(&nfc->chips);
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index e6b14b79c8a829c401e05445a5459ca6a932dbcc..7bc6be3f6ec0b9b71fb2c2862090e4e0b8a859f4 100644 (file)
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -145,7 +145,7 @@ struct mtk_nfc_clk {
 };
 
 struct mtk_nfc {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct mtk_ecc_config ecc_cfg;
        struct mtk_nfc_clk clk;
        struct mtk_ecc *ecc;

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index e545e03a214e5f6d4b31088733fb634977df0f18..dcdf0f373100a31a40c7d64a0609d54c8e35ccd4 100644 (file)
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5000,8 +5000,8 @@ static void nand_set_defaults(struct nand_chip *chip)
                chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
 
        if (!chip->controller) {
-               chip->controller = &chip->hwcontrol;
-               nand_hw_control_init(chip->controller);
+               chip->controller = &chip->dummy_controller;
+               nand_controller_init(chip->controller);
        }
 
        if (!chip->buf_align)

diff --git a/drivers/mtd/nand/raw/ndfc.c b/drivers/mtd/nand/raw/ndfc.c
index d8a806894937660dce9defd2fdf35c5a3c654126..540fa1a0ea24ec5605231bb2946cd782c71fab1b 100644 (file)
--- a/drivers/mtd/nand/raw/ndfc.c
+++ b/drivers/mtd/nand/raw/ndfc.c
@@ -39,7 +39,7 @@ struct ndfc_controller {
        void __iomem *ndfcbase;
        struct nand_chip chip;
        int chip_select;
-       struct nand_hw_control ndfc_control;
+       struct nand_controller ndfc_control;
 };
 
 static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
@@ -218,7 +218,7 @@ static int ndfc_probe(struct platform_device *ofdev)
        ndfc = &ndfc_ctrl[cs];
        ndfc->chip_select = cs;
 
-       nand_hw_control_init(&ndfc->ndfc_control);
+       nand_controller_init(&ndfc->ndfc_control);
        ndfc->ofdev = ofdev;
        dev_set_drvdata(&ofdev->dev, ndfc);
 

diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c
index e50c64adc3c842bfa7cc6f68db08245a92f927ea..e943b2e5a5e2e92ed2e765aec52e1306d5b3c24e 100644 (file)
--- a/drivers/mtd/nand/raw/omap2.c
+++ b/drivers/mtd/nand/raw/omap2.c
@@ -145,7 +145,7 @@ static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 
 /* Shared among all NAND instances to synchronize access to the ECC Engine */
-static struct nand_hw_control omap_gpmc_controller = {
+static struct nand_controller omap_gpmc_controller = {
        .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
        .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
 };

diff --git a/drivers/mtd/nand/raw/oxnas_nand.c b/drivers/mtd/nand/raw/oxnas_nand.c
index d649d5944826ef9005a495720e1c0a5966147da5..01b00bb69c1e60889af64aaa8b461f085b447347 100644 (file)
--- a/drivers/mtd/nand/raw/oxnas_nand.c
+++ b/drivers/mtd/nand/raw/oxnas_nand.c
@@ -32,7 +32,7 @@
 #define OXNAS_NAND_MAX_CHIPS   1
 
 struct oxnas_nand_ctrl {
-       struct nand_hw_control base;
+       struct nand_controller base;
        void __iomem *io_base;
        struct clk *clk;
        struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
@@ -96,7 +96,7 @@ static int oxnas_nand_probe(struct platform_device *pdev)
        if (!oxnas)
                return -ENOMEM;
 
-       nand_hw_control_init(&oxnas->base);
+       nand_controller_init(&oxnas->base);
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 645630953f3880a17ef984426c840ae6c98786e6..aa6c3e026ef19cfbd14e15cfe9ee294205a83426 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -365,7 +365,7 @@ struct nandc_regs {
  *                             from all connected NAND devices pagesize
  */
 struct qcom_nand_controller {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct list_head host_list;
 
        struct device *dev;
@@ -2728,7 +2728,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
        INIT_LIST_HEAD(&nandc->desc_list);
        INIT_LIST_HEAD(&nandc->host_list);
 
-       nand_hw_control_init(&nandc->controller);
+       nand_controller_init(&nandc->controller);
 
        return 0;
 }

diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c
index 5a4a68790653163fd411502579756f2736fbcf78..e8bf64832213c90424db034ddb6d220bdbffca10 100644 (file)
--- a/drivers/mtd/nand/raw/s3c2410.c
+++ b/drivers/mtd/nand/raw/s3c2410.c
@@ -162,7 +162,7 @@ enum s3c_nand_clk_state {
  */
 struct s3c2410_nand_info {
        /* mtd info */
-       struct nand_hw_control          controller;
+       struct nand_controller          controller;
        struct s3c2410_nand_mtd         *mtds;
        struct s3c2410_platform_nand    *platform;
 
@@ -1094,7 +1094,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
 
        platform_set_drvdata(pdev, info);
 
-       nand_hw_control_init(&info->controller);
+       nand_controller_init(&info->controller);
 
        /* get the clock source and enable it */
 

diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index 4b11cd4a79be2eb9f3b922def5b8fd4bd0be7eac..07f3ff9a28f23b3044b4fdb73a5152e1d0723679 100644 (file)
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -234,7 +234,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
  *                     controller events
  */
 struct sunxi_nfc {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct device *dev;
        void __iomem *regs;
        struct clk *ahb_clk;
@@ -247,7 +247,7 @@ struct sunxi_nfc {
        struct dma_chan *dmac;
 };
 
-static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
+static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_controller *ctrl)
 {
        return container_of(ctrl, struct sunxi_nfc, controller);
 }
@@ -2012,7 +2012,7 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
                return -ENOMEM;
 
        nfc->dev = dev;
-       nand_hw_control_init(&nfc->controller);
+       nand_controller_init(&nfc->controller);
        INIT_LIST_HEAD(&nfc->chips);
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

diff --git a/drivers/mtd/nand/raw/tango_nand.c b/drivers/mtd/nand/raw/tango_nand.c
index f2052fae21c7453ae6f5fa3698fd2d38fa1884ad..dd7a26efdf4fd8fa41bf53b0457b3434e41728f1 100644 (file)
--- a/drivers/mtd/nand/raw/tango_nand.c
+++ b/drivers/mtd/nand/raw/tango_nand.c
@@ -83,7 +83,7 @@
 #define MAX_CS         4
 
 struct tango_nfc {
-       struct nand_hw_control hw;
+       struct nand_controller hw;
        void __iomem *reg_base;
        void __iomem *mem_base;
        void __iomem *pbus_base;
@@ -654,7 +654,7 @@ static int tango_nand_probe(struct platform_device *pdev)
                return PTR_ERR(nfc->chan);
 
        platform_set_drvdata(pdev, nfc);
-       nand_hw_control_init(&nfc->hw);
+       nand_controller_init(&nfc->hw);
        nfc->freq_kHz = clk_get_rate(clk) / 1000;
 
        for_each_child_of_node(pdev->dev.of_node, np) {

diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
index 56c0aa1bc81f9b617a8858cf477185d5e18b4b1d..31c0d9ca9d2374d0862d3ec708daa7f3891b1fda 100644 (file)
--- a/drivers/mtd/nand/raw/tegra_nand.c
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -164,7 +164,7 @@
                                HWSTATUS_RBSY_VALUE(NAND_STATUS_READY))
 
 struct tegra_nand_controller {
-       struct nand_hw_control controller;
+       struct nand_controller controller;
        struct device *dev;
        void __iomem *regs;
        int irq;
@@ -187,7 +187,7 @@ struct tegra_nand_chip {
 };
 
 static inline struct tegra_nand_controller *
-                       to_tegra_ctrl(struct nand_hw_control *hw_ctrl)
+                       to_tegra_ctrl(struct nand_controller *hw_ctrl)
 {
        return container_of(hw_ctrl, struct tegra_nand_controller, controller);
 }
@@ -1136,7 +1136,7 @@ static int tegra_nand_probe(struct platform_device *pdev)
                return -ENOMEM;
 
        ctrl->dev = &pdev->dev;
-       nand_hw_control_init(&ctrl->controller);
+       nand_controller_init(&ctrl->controller);
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        ctrl->regs = devm_ioremap_resource(&pdev->dev, res);

diff --git a/drivers/mtd/nand/raw/txx9ndfmc.c b/drivers/mtd/nand/raw/txx9ndfmc.c
index 5fe9da8b4a0afcad7a2333d561220d5449a15f77..8f5bbbac461284eb41e071557bc2bca8feddd4cc 100644 (file)
--- a/drivers/mtd/nand/raw/txx9ndfmc.c
+++ b/drivers/mtd/nand/raw/txx9ndfmc.c
@@ -73,7 +73,7 @@ struct txx9ndfmc_drvdata {
        void __iomem *base;
        unsigned char hold;     /* in gbusclock */
        unsigned char spw;      /* in gbusclock */
-       struct nand_hw_control hw_control;
+       struct nand_controller hw_control;
 };
 
 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
@@ -303,7 +303,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
        dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
                 (gbusclk + 500000) / 1000000, hold, spw);
 
-       nand_hw_control_init(&drvdata->hw_control);
+       nand_controller_init(&drvdata->hw_control);
 
        platform_set_drvdata(dev, drvdata);
        txx9ndfmc_initialize(dev);

diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 598d356de83f58b06d0421d5f8e3f30f7f1f09ed..93a2678e0f0d7be973b151b55a161df132fe5a6c 100644 (file)
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -510,20 +510,21 @@ struct nand_id {
 };
 
 /**
- * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
+ * struct nand_controller - Structure used to describe a NAND controller
+ *
  * @lock:               protection lock
  * @active:            the mtd device which holds the controller currently
  * @wq:                        wait queue to sleep on if a NAND operation is in
  *                     progress used instead of the per chip wait queue
  *                     when a hw controller is available.
  */
-struct nand_hw_control {
+struct nand_controller {
        spinlock_t lock;
        struct nand_chip *active;
        wait_queue_head_t wq;
 };
 
-static inline void nand_hw_control_init(struct nand_hw_control *nfc)
+static inline void nand_controller_init(struct nand_controller *nfc)
 {
        nfc->active = NULL;
        spin_lock_init(&nfc->lock);
@@ -1197,7 +1198,8 @@ int nand_op_parser_exec_op(struct nand_chip *chip,
  *                     setting the read-retry mode. Mostly needed for MLC NAND.
  * @ecc:               [BOARDSPECIFIC] ECC control structure
  * @buf_align:         minimum buffer alignment required by a platform
- * @hwcontrol:         platform-specific hardware control structure
+ * @dummy_controller:  dummy controller implementation for drivers that can
+ *                     only control a single chip
  * @erase:             [REPLACEABLE] erase function
  * @chip_delay:                [BOARDSPECIFIC] chip dependent delay for transferring
  *                     data from array to read regs (tR).
@@ -1333,11 +1335,11 @@ struct nand_chip {
        flstate_t state;
 
        uint8_t *oob_poi;
-       struct nand_hw_control *controller;
+       struct nand_controller *controller;
 
        struct nand_ecc_ctrl ecc;
        unsigned long buf_align;
-       struct nand_hw_control hwcontrol;
+       struct nand_controller dummy_controller;
 
        uint8_t *bbt;
        struct nand_bbt_descr *bbt_td;