drm/i915: Extract ilk_pch_get_config()

Pull the ilk+ PCH state readout into its own function and relocate
to the appropriate file.

The clock readout parts are perhaps a bit iffy since we depend
on the gmch DPLL readout code. But we can think about the clock
readout big picture later.

Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211015071625.593-6-ville.syrjala@linux.intel.com
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 482498188c6cc6576ffaad508b17fcb22c86682f..9bac7418fe3fc33b124960e0b0f2d4221536d0a6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -111,11 +111,6 @@
 #include "skl_universal_plane.h"
 #include "vlv_sideband.h"
 
-static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
-                               struct intel_crtc_state *pipe_config);
-static void ilk_pch_clock_get(struct intel_crtc *crtc,
-                             struct intel_crtc_state *pipe_config);
-
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -4226,50 +4221,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
        i9xx_get_pipe_color_config(pipe_config);
        intel_color_get_config(pipe_config);
 
-       if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
-               struct intel_shared_dpll *pll;
-               enum intel_dpll_id pll_id;
-               bool pll_active;
-
-               pipe_config->has_pch_encoder = true;
-
-               tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
-               pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
-                                         FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
-               ilk_get_fdi_m_n_config(crtc, pipe_config);
-
-               if (HAS_PCH_IBX(dev_priv)) {
-                       /*
-                        * The pipe->pch transcoder and pch transcoder->pll
-                        * mapping is fixed.
-                        */
-                       pll_id = (enum intel_dpll_id) crtc->pipe;
-               } else {
-                       tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
-                       if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
-                               pll_id = DPLL_ID_PCH_PLL_B;
-                       else
-                               pll_id= DPLL_ID_PCH_PLL_A;
-               }
-
-               pipe_config->shared_dpll =
-                       intel_get_shared_dpll_by_id(dev_priv, pll_id);
-               pll = pipe_config->shared_dpll;
-
-               pll_active = intel_dpll_get_hw_state(dev_priv, pll,
-                                                    &pipe_config->dpll_hw_state);
-               drm_WARN_ON(dev, !pll_active);
-
-               tmp = pipe_config->dpll_hw_state.dpll;
-               pipe_config->pixel_multiplier =
-                       ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
-                        >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+       pipe_config->pixel_multiplier = 1;
 
-               ilk_pch_clock_get(crtc, pipe_config);
-       } else {
-               pipe_config->pixel_multiplier = 1;
-       }
+       ilk_pch_get_config(pipe_config);
 
        intel_get_transcoder_timings(crtc, pipe_config);
        intel_get_pipe_src_size(crtc, pipe_config);
@@ -4852,8 +4806,8 @@ static int i9xx_pll_refclk(struct drm_device *dev,
 }
 
 /* Returns the clock of the currently programmed mode of the given pipe. */
-static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
-                               struct intel_crtc_state *pipe_config)
+void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+                        struct intel_crtc_state *pipe_config)
 {
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4963,24 +4917,6 @@ int intel_dotclock_calculate(int link_freq,
        return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
 }
 
-static void ilk_pch_clock_get(struct intel_crtc *crtc,
-                             struct intel_crtc_state *pipe_config)
-{
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-       /* read out port_clock from the DPLL */
-       i9xx_crtc_clock_get(crtc, pipe_config);
-
-       /*
-        * In case there is an active pipe without active ports,
-        * we may need some idea for the dotclock anyway.
-        * Calculate one based on the FDI configuration.
-        */
-       pipe_config->hw.adjusted_mode.crtc_clock =
-               intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
-                                        &pipe_config->fdi_m_n);
-}
-
 /* Returns the currently programmed mode of the given encoder. */
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 5bc8d891317853dcd714ca43bf99a49c8c910d01..c2efba7c6c172966a0506bec6009c4b71707299d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -586,8 +586,9 @@ void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
                      enum link_m_n_set m_n);
 void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
                            struct intel_crtc_state *pipe_config);
+void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+                        struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
-
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index b4c6557ba8b93e8b3d1073c848a510e0f4d52ad6..13685c192932211e823cd5e6a7f1237fc7d53086 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -299,6 +299,74 @@ void ilk_pch_enable(struct intel_atomic_state *state,
        ilk_enable_pch_transcoder(crtc_state);
 }
 
+static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+       /* read out port_clock from the DPLL */
+       i9xx_crtc_clock_get(crtc, crtc_state);
+
+       /*
+        * In case there is an active pipe without active ports,
+        * we may need some idea for the dotclock anyway.
+        * Calculate one based on the FDI configuration.
+        */
+       crtc_state->hw.adjusted_mode.crtc_clock =
+               intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
+                                        &crtc_state->fdi_m_n);
+}
+
+void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       struct intel_shared_dpll *pll;
+       enum pipe pipe = crtc->pipe;
+       enum intel_dpll_id pll_id;
+       bool pll_active;
+       u32 tmp;
+
+       if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
+               return;
+
+       crtc_state->has_pch_encoder = true;
+
+       tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
+       crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+                                FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+       ilk_get_fdi_m_n_config(crtc, crtc_state);
+
+       if (HAS_PCH_IBX(dev_priv)) {
+               /*
+                * The pipe->pch transcoder and pch transcoder->pll
+                * mapping is fixed.
+                */
+               pll_id = (enum intel_dpll_id) pipe;
+       } else {
+               tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+               if (tmp & TRANS_DPLLB_SEL(pipe))
+                       pll_id = DPLL_ID_PCH_PLL_B;
+               else
+                       pll_id = DPLL_ID_PCH_PLL_A;
+       }
+
+       crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+       pll = crtc_state->shared_dpll;
+
+       pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+                                            &crtc_state->dpll_hw_state);
+       drm_WARN_ON(&dev_priv->drm, !pll_active);
+
+       tmp = crtc_state->dpll_hw_state.dpll;
+       crtc_state->pixel_multiplier =
+               ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
+                >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+
+       ilk_pch_clock_get(crtc_state);
+}
+
 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
                                      enum transcoder cpu_transcoder)
 {

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index e0ff331c0bc6d6c4c8b969d5c391c3e6b3f43c09..6e834fbebd64ad9c8f58fa3363cdf2904fdc4f79 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -14,6 +14,7 @@ struct intel_crtc_state;
 void ilk_disable_pch_transcoder(struct intel_crtc *crtc);
 void ilk_pch_enable(struct intel_atomic_state *state,
                    struct intel_crtc *crtc);
+void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
 
 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
 void lpt_pch_enable(struct intel_atomic_state *state,