MIPS: CM3: Add support for CM3 L2 cache.

Detect the L2 cache configuration from GCR_L2_CONFIG when a CM3 is
present in the system, rather than from Config2 which does not expose
the L2 configuration on I6400.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10641/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 4ceafd13870cd6945634713f04ac3f7d65ba52d2..5fa452e8cff923bfa54807769e9f5a05800549d8 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -14,6 +14,7 @@
 #include <asm/pgtable.h>
 #include <asm/mmu_context.h>
 #include <asm/r4kcache.h>
+#include <asm/mips-cm.h>
 
 /*
  * MIPS32/MIPS64 L2 cache handling
@@ -94,6 +95,34 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
        return 1;
 }
 
+static int __init mips_sc_probe_cm3(void)
+{
+       struct cpuinfo_mips *c = &current_cpu_data;
+       unsigned long cfg = read_gcr_l2_config();
+       unsigned long sets, line_sz, assoc;
+
+       if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK)
+               return 0;
+
+       sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
+       sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
+       c->scache.sets = 64 << sets;
+
+       line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
+       line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
+       c->scache.linesz = 2 << line_sz;
+
+       assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
+       assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
+       c->scache.ways = assoc + 1;
+       c->scache.waysize = c->scache.sets * c->scache.linesz;
+       c->scache.waybit = __ffs(c->scache.waysize);
+
+       c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+
+       return 1;
+}
+
 static inline int __init mips_sc_probe(void)
 {
        struct cpuinfo_mips *c = &current_cpu_data;
@@ -103,6 +132,9 @@ static inline int __init mips_sc_probe(void)
        /* Mark as not present until probe completed */
        c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
 
+       if (mips_cm_revision() >= CM_REV_CM3)
+               return mips_sc_probe_cm3();
+
        /* Ignore anything but MIPSxx processors */
        if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
                              MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |