net/mlx5: Free used cpus mask when an IRQ is released

Each EQ table maintains a cpumask of the already used CPUs that are mapped
to IRQs to ensure that each IRQ gets mapped to a unique CPU.

However, on IRQ release, the said cpumask is not updated by clearing the
CPU from the mask to allow future IRQ request, causing the following
error when a SF is reloaded after it has utilized all CPUs for its IRQs:

mlx5_irq_affinity_request:135:(pid 306010): Didn't find a matching IRQ.
err = -28

Thus, when releasing an IRQ, clear its mapped CPU from the used CPUs
mask, to prevent the case described above.

While at it, move the used cpumask update to the EQ layer as it is more
fitting and preserves symmetricity of the IRQ request/release API.

Fixes: a1772de78d73 ("net/mlx5: Refactor completion IRQ request/release API")
Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Link: https://lore.kernel.org/r/20231114215846.5902-3-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index ea0405e0a43facbae35f5d0ebe4bb01f144b2a56..40a6cb052a2da3f4c0e272202b3bd1466053a5ad 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@ -885,11 +885,14 @@ static void comp_irq_release_sf(struct mlx5_core_dev *dev, u16 vecidx)
 {
        struct mlx5_eq_table *table = dev->priv.eq_table;
        struct mlx5_irq *irq;
+       int cpu;
 
        irq = xa_load(&table->comp_irqs, vecidx);
        if (!irq)
                return;
 
+       cpu = cpumask_first(mlx5_irq_get_affinity_mask(irq));
+       cpumask_clear_cpu(cpu, &table->used_cpus);
        xa_erase(&table->comp_irqs, vecidx);
        mlx5_irq_affinity_irq_release(dev, irq);
 }
@@ -897,16 +900,26 @@ static void comp_irq_release_sf(struct mlx5_core_dev *dev, u16 vecidx)
 static int comp_irq_request_sf(struct mlx5_core_dev *dev, u16 vecidx)
 {
        struct mlx5_eq_table *table = dev->priv.eq_table;
+       struct mlx5_irq_pool *pool = mlx5_irq_pool_get(dev);
+       struct irq_affinity_desc af_desc = {};
        struct mlx5_irq *irq;
 
-       irq = mlx5_irq_affinity_irq_request_auto(dev, &table->used_cpus, vecidx);
-       if (IS_ERR(irq)) {
-               /* In case SF irq pool does not exist, fallback to the PF irqs*/
-               if (PTR_ERR(irq) == -ENOENT)
-                       return comp_irq_request_pci(dev, vecidx);
+       /* In case SF irq pool does not exist, fallback to the PF irqs*/
+       if (!mlx5_irq_pool_is_sf_pool(pool))
+               return comp_irq_request_pci(dev, vecidx);
 
+       af_desc.is_managed = 1;
+       cpumask_copy(&af_desc.mask, cpu_online_mask);
+       cpumask_andnot(&af_desc.mask, &af_desc.mask, &table->used_cpus);
+       irq = mlx5_irq_affinity_request(pool, &af_desc);
+       if (IS_ERR(irq))
                return PTR_ERR(irq);
-       }
+
+       cpumask_or(&table->used_cpus, &table->used_cpus, mlx5_irq_get_affinity_mask(irq));
+       mlx5_core_dbg(pool->dev, "IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n",
+                     pci_irq_vector(dev->pdev, mlx5_irq_get_index(irq)),
+                     cpumask_pr_args(mlx5_irq_get_affinity_mask(irq)),
+                     mlx5_irq_read_locked(irq) / MLX5_EQ_REFS_PER_IRQ);
 
        return xa_err(xa_store(&table->comp_irqs, vecidx, irq, GFP_KERNEL));
 }

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
index 047d5fed5f89e62cb58c4e9f8d2e094247430a16..612e666ec2635614f2e24443f319efd822b369b5 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
@@ -168,45 +168,3 @@ void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *i
                if (pool->irqs_per_cpu)
                        cpu_put(pool, cpu);
 }
-
-/**
- * mlx5_irq_affinity_irq_request_auto - request one IRQ for mlx5 device.
- * @dev: mlx5 device that is requesting the IRQ.
- * @used_cpus: cpumask of bounded cpus by the device
- * @vecidx: vector index to request an IRQ for.
- *
- * Each IRQ is bounded to at most 1 CPU.
- * This function is requesting an IRQ according to the default assignment.
- * The default assignment policy is:
- * - request the least loaded IRQ which is not bound to any
- *   CPU of the previous IRQs requested.
- *
- * On success, this function updates used_cpus mask and returns an irq pointer.
- * In case of an error, an appropriate error pointer is returned.
- */
-struct mlx5_irq *mlx5_irq_affinity_irq_request_auto(struct mlx5_core_dev *dev,
-                                                   struct cpumask *used_cpus, u16 vecidx)
-{
-       struct mlx5_irq_pool *pool = mlx5_irq_pool_get(dev);
-       struct irq_affinity_desc af_desc = {};
-       struct mlx5_irq *irq;
-
-       if (!mlx5_irq_pool_is_sf_pool(pool))
-               return ERR_PTR(-ENOENT);
-
-       af_desc.is_managed = 1;
-       cpumask_copy(&af_desc.mask, cpu_online_mask);
-       cpumask_andnot(&af_desc.mask, &af_desc.mask, used_cpus);
-       irq = mlx5_irq_affinity_request(pool, &af_desc);
-
-       if (IS_ERR(irq))
-               return irq;
-
-       cpumask_or(used_cpus, used_cpus, mlx5_irq_get_affinity_mask(irq));
-       mlx5_core_dbg(pool->dev, "IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n",
-                     pci_irq_vector(dev->pdev, mlx5_irq_get_index(irq)),
-                     cpumask_pr_args(mlx5_irq_get_affinity_mask(irq)),
-                     mlx5_irq_read_locked(irq) / MLX5_EQ_REFS_PER_IRQ);
-
-       return irq;
-}