* Definitions for 7:0 on legacy processors
  */
 
-#define PRID_REV_TX4927                0x0022
-#define PRID_REV_TX4937                0x0030
-#define PRID_REV_R4400         0x0040
-#define PRID_REV_R3000A                0x0030
-#define PRID_REV_R3000         0x0020
-#define PRID_REV_R2000A                0x0010
-#define PRID_REV_TX3912                0x0010
-#define PRID_REV_TX3922                0x0030
-#define PRID_REV_TX3927                0x0040
-#define PRID_REV_VR4111                0x0050
-#define PRID_REV_VR4181                0x0050  /* Same as VR4111 */
-#define PRID_REV_VR4121                0x0060
-#define PRID_REV_VR4122                0x0070
-#define PRID_REV_VR4181A       0x0070  /* Same as VR4122 */
-#define PRID_REV_VR4130                0x0080
-#define PRID_REV_34K_V1_0_2    0x0022
-#define PRID_REV_LOONGSON1B    0x0020
-#define PRID_REV_LOONGSON1C    0x0020  /* Same as Loongson-1B */
-#define PRID_REV_LOONGSON2E    0x0002
-#define PRID_REV_LOONGSON2F    0x0003
-#define PRID_REV_LOONGSON3A_R1 0x0005
-#define PRID_REV_LOONGSON3B_R1 0x0006
-#define PRID_REV_LOONGSON3B_R2 0x0007
-#define PRID_REV_LOONGSON3A_R2 0x0008
-#define PRID_REV_LOONGSON3A_R3 0x0009
+#define PRID_REV_TX4927                        0x0022
+#define PRID_REV_TX4937                        0x0030
+#define PRID_REV_R4400                 0x0040
+#define PRID_REV_R3000A                        0x0030
+#define PRID_REV_R3000                 0x0020
+#define PRID_REV_R2000A                        0x0010
+#define PRID_REV_TX3912                        0x0010
+#define PRID_REV_TX3922                        0x0030
+#define PRID_REV_TX3927                        0x0040
+#define PRID_REV_VR4111                        0x0050
+#define PRID_REV_VR4181                        0x0050  /* Same as VR4111 */
+#define PRID_REV_VR4121                        0x0060
+#define PRID_REV_VR4122                        0x0070
+#define PRID_REV_VR4181A               0x0070  /* Same as VR4122 */
+#define PRID_REV_VR4130                        0x0080
+#define PRID_REV_34K_V1_0_2            0x0022
+#define PRID_REV_LOONGSON1B            0x0020
+#define PRID_REV_LOONGSON1C            0x0020  /* Same as Loongson-1B */
+#define PRID_REV_LOONGSON2E            0x0002
+#define PRID_REV_LOONGSON2F            0x0003
+#define PRID_REV_LOONGSON3A_R1         0x0005
+#define PRID_REV_LOONGSON3B_R1         0x0006
+#define PRID_REV_LOONGSON3B_R2         0x0007
+#define PRID_REV_LOONGSON3A_R2         0x0008
+#define PRID_REV_LOONGSON3A_R3_0       0x0009
+#define PRID_REV_LOONGSON3A_R3_1       0x000d
 
 /*
  * Older processors used to encode processor version and revision in two