ASoC: SOF: amd: Move group register configuration to acp-loader

We are using PTE_GRP1 for DMA operations to load firmware binaries
but we are enabling PTE_GRP and flushing ATU cache much before in
probe callbacks. This can cause issue if we try to load firmware
runtime during system resume as probe callback will not be invoked
hence PTE_GRP will not be enabled. Moreover it makes more sense to
flush the cache after register configuration.

Move PTE group register configuration to acp-loader within pre_fw_run
callback to avoid such issue.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220304205733.62233-7-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sof/amd/acp-loader.c b/sound/soc/sof/amd/acp-loader.c
index 2dc15ae3815524310d5e87e52c41762fbd4e52cc..7ca51e0f3b1b19bedf0be5b11913ce6b0213fc99 100644 (file)
--- a/sound/soc/sof/amd/acp-loader.c
+++ b/sound/soc/sof/amd/acp-loader.c
@@ -127,6 +127,12 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev
                return;
        }
 
+       /* Group Enable */
+       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
+                         ACP_SRAM_PTE_OFFSET | BIT(31));
+       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
+                         PAGE_SIZE_4K_ENABLE);
+
        for (page_idx = 0; page_idx < num_pages; page_idx++) {
                low = lower_32_bits(addr);
                high = upper_32_bits(addr);
@@ -136,6 +142,9 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev
                offset += 8;
                addr += PAGE_SIZE;
        }
+
+       /* Flush ATU Cache after PTE Update */
+       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
 }
 
 /* pre fw run operations */

diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c
index ba8b6427b59f13909dde480f00e849a3c04e1230..66ca05545be27c4d4bca47a4e20ac5b65720657c 100644 (file)
--- a/sound/soc/sof/amd/acp.c
+++ b/sound/soc/sof/amd/acp.c
@@ -36,19 +36,6 @@ static int smn_read(struct pci_dev *dev, u32 smn_addr, u32 *data)
        return 0;
 }
 
-static void configure_acp_groupregisters(struct acp_dev_data *adata)
-{
-       struct snd_sof_dev *sdev = adata->dev;
-
-       /* Group Enable */
-       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
-                         ACP_SRAM_PTE_OFFSET | BIT(31));
-       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
-                         PAGE_SIZE_4K_ENABLE);
-
-       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
-}
-
 static void init_dma_descriptor(struct acp_dev_data *adata)
 {
        struct snd_sof_dev *sdev = adata->dev;
@@ -264,7 +251,6 @@ static int acp_memory_init(struct snd_sof_dev *sdev)
 
        snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_CNTL,
                                ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
-       configure_acp_groupregisters(adata);
        init_dma_descriptor(adata);
 
        return 0;